mirror of https://github.com/acidanthera/audk.git
305 lines
10 KiB
C
305 lines
10 KiB
C
/** @file
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* Main file supporting the SEC Phase for Versatile Express
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PrintLib.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/ArmLib.h>
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#include <Library/SerialPortLib.h>
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#include <Library/ArmPlatformLib.h>
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#include <Chipset/ArmV7.h>
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#include <Drivers/PL390Gic.h>
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#define ARM_PRIMARY_CORE 0
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#define SerialPrint(txt) SerialPortWrite (txt, AsciiStrLen(txt)+1);
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extern VOID *monitor_vector_table;
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VOID
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ArmSetupGicNonSecure (
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IN INTN GicDistributorBase,
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IN INTN GicInterruptInterfaceBase
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);
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// Vector Table for Sec Phase
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VOID
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SecVectorTable (
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VOID
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);
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VOID
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NonSecureWaitForFirmware (
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VOID
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);
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VOID
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enter_monitor_mode(
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IN VOID* Stack
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);
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VOID
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return_from_exception (
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IN UINTN NonSecureBase
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);
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VOID
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copy_cpsr_into_spsr (
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VOID
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);
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VOID
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CEntryPoint (
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IN UINTN CoreId
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)
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{
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CHAR8 Buffer[100];
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UINTN CharCount;
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// Primary CPU clears out the SCU tag RAMs, secondaries wait
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if (CoreId == ARM_PRIMARY_CORE) {
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if (FixedPcdGet32(PcdMPCoreSupport)) {
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ArmInvalidScu();
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}
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// SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib
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// In non SEC modules the init call is in autogenerated code.
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SerialPortInitialize ();
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// Start talking
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CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware built at %a on %a\n\r",__TIME__, __DATE__);
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SerialPortWrite ((UINT8 *) Buffer, CharCount);
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// Now we've got UART, make the check:
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// - The Vector table must be 32-byte aligned
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ASSERT(((UINT32)SecVectorTable & ((1 << 5)-1)) == 0);
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}
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// Invalidate the data cache. Doesn't have to do the Data cache clean.
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ArmInvalidateDataCache();
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//Invalidate Instruction Cache
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ArmInvalidateInstructionCache();
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//Invalidate I & D TLBs
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ArmInvalidateInstructionAndDataTlb();
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// Enable Full Access to CoProcessors
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ArmWriteCPACR (CPACR_CP_FULL_ACCESS);
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// Enable SWP instructions
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ArmEnableSWPInstruction();
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// Enable program flow prediction, if supported.
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ArmEnableBranchPrediction();
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if (FixedPcdGet32(PcdVFPEnabled)) {
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ArmEnableVFP();
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}
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if (CoreId == ARM_PRIMARY_CORE) {
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// Initialize peripherals that must be done at the early stage
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// Example: Some L2x0 controllers must be initialized in Secure World
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ArmPlatformSecInitialize ();
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// If we skip the PEI Core we could want to initialize the DRAM in the SEC phase.
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// If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM
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if (FeaturePcdGet(PcdSkipPeiCore) || !FeaturePcdGet(PcdStandalone)) {
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// Initialize system memory (DRAM)
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ArmPlatformInitializeSystemMemory ();
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}
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// Some platform can change their physical memory mapping
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ArmPlatformBootRemapping ();
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}
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// Test if Trustzone is supported on this platform
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if (ArmPlatformTrustzoneSupported()) {
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if (FixedPcdGet32(PcdMPCoreSupport)) {
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// Setup SMP in Non Secure world
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ArmSetupSmpNonSecure (CoreId);
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}
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// Enter Monitor Mode
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enter_monitor_mode((VOID*)(PcdGet32(PcdCPUCoresSecMonStackBase) + (PcdGet32(PcdCPUCoreSecMonStackSize) * CoreId)));
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//Write the monitor mode vector table address
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ArmWriteVMBar((UINT32) &monitor_vector_table);
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//-------------------- Monitor Mode ---------------------
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// Setup the Trustzone Chipsets
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if (CoreId == ARM_PRIMARY_CORE) {
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ArmPlatformTrustzoneInit();
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// Wake up the secondary cores by sending a interrupt to everyone else
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// NOTE 1: The Software Generated Interrupts are always enabled on Cortex-A9
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// MPcore test chip on Versatile Express board, So the Software doesn't have to
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// enable SGI's explicitly.
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// 2: As no other Interrupts are enabled, doesn't have to worry about the priority.
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// 3: As all the cores are in secure state, use secure SGI's
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//
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PL390GicEnableDistributor (PcdGet32(PcdGicDistributorBase));
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PL390GicEnableInterruptInterface(PcdGet32(PcdGicInterruptInterfaceBase));
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// Send SGI to all Secondary core to wake them up from WFI state.
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PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
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} else {
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// The secondary cores need to wait until the Trustzone chipsets configuration is done
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// before switching to Non Secure World
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// Enabled GIC CPU Interface
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PL390GicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
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// Waiting for the SGI from the primary core
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ArmCallWFI();
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// Acknowledge the interrupt and send End of Interrupt signal.
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PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase), ARM_PRIMARY_CORE);
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}
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// Transfer the interrupt to Non-secure World
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PL390GicSetupNonSecure(PcdGet32(PcdGicDistributorBase),PcdGet32(PcdGicInterruptInterfaceBase));
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// Write to CP15 Non-secure Access Control Register :
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// - Enable CP10 and CP11 accesses in NS World
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// - Enable Access to Preload Engine in NS World
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// - Enable lockable TLB entries allocation in NS world
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// - Enable R/W access to SMP bit of Auxiliary Control Register in NS world
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ArmWriteNsacr(NSACR_NS_SMP | NSACR_TL | NSACR_PLE | NSACR_CP(10) | NSACR_CP(11));
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// CP15 Secure Configuration Register with Non Secure bit (SCR_NS), CPSR.A modified in any
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// security state (SCR_AW), CPSR.F modified in any security state (SCR_FW)
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ArmWriteScr(SCR_NS | SCR_FW | SCR_AW);
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} else {
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if (CoreId == ARM_PRIMARY_CORE) {
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SerialPrint ("Trust Zone Configuration is disabled\n\r");
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}
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// Trustzone is not enabled, just enable the Distributor and CPU interface
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if (CoreId == ARM_PRIMARY_CORE) {
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PL390GicEnableDistributor (PcdGet32(PcdGicDistributorBase));
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}
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PL390GicEnableInterruptInterface(PcdGet32(PcdGicInterruptInterfaceBase));
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// With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
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// If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
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// Status Register as the the current one (CPSR).
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copy_cpsr_into_spsr();
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}
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// If ArmVe has not been built as Standalone then we need to patch the DRAM to add an infinite loop at the start address
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if (FeaturePcdGet(PcdStandalone) == FALSE) {
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if (CoreId == ARM_PRIMARY_CORE) {
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UINTN* StartAddress = (UINTN*)PcdGet32(PcdNormalFvBaseAddress);
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// Patch the DRAM to make an infinite loop at the start address
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*StartAddress = 0xEAFFFFFE; // opcode for while(1)
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CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Waiting for firmware at 0x%08X ...\n\r",StartAddress);
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SerialPortWrite ((UINT8 *) Buffer, CharCount);
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// To enter into Non Secure state, we need to make a return from exception
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return_from_exception(PcdGet32(PcdNormalFvBaseAddress));
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} else {
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// When the primary core is stopped by the hardware debugger to copy the firmware
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// into DRAM. The secondary cores are still running. As soon as the first bytes of
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// the firmware are written into DRAM, the secondary cores will start to execute the
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// code even if the firmware is not entirely written into the memory.
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// That's why the secondary cores need to be parked in WFI and wake up once the
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// firmware is ready.
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// Enter Secondary Cores into non Secure State. To enter into Non Secure state, we need to make a return from exception
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return_from_exception((UINTN)NonSecureWaitForFirmware);
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}
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} else {
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// To enter into Non Secure state, we need to make a return from exception
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return_from_exception(PcdGet32(PcdNormalFvBaseAddress));
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}
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//-------------------- Non Secure Mode ---------------------
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// PEI Core should always load and never return
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ASSERT (FALSE);
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}
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// When the firmware is built as not Standalone, the secondary cores need to wait the firmware
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// entirely written into DRAM. It is the firmware from DRAM which will wake up the secondary cores.
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VOID
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NonSecureWaitForFirmware (
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VOID
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)
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{
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VOID (*secondary_start)(VOID);
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// The secondary cores will execute the firmware once wake from WFI.
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secondary_start = (VOID (*)())PcdGet32(PcdNormalFvBaseAddress);
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ArmCallWFI();
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// Acknowledge the interrupt and send End of Interrupt signal.
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PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),ARM_PRIMARY_CORE);
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// Jump to secondary core entry point.
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secondary_start();
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// PEI Core should always load and never return
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ASSERT (FALSE);
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}
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VOID
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SecCommonExceptionEntry (
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IN UINT32 Entry,
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IN UINT32 LR
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)
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{
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CHAR8 Buffer[100];
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UINTN CharCount;
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switch (Entry) {
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case 0:
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CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reset Exception at 0x%X\n\r",LR);
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break;
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case 1:
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CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Undefined Exception at 0x%X\n\r",LR);
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break;
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case 2:
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CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SWI Exception at 0x%X\n\r",LR);
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break;
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case 3:
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CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"PrefetchAbort Exception at 0x%X\n\r",LR);
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break;
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case 4:
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CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"DataAbort Exception at 0x%X\n\r",LR);
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break;
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case 5:
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CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reserved Exception at 0x%X\n\r",LR);
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break;
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case 6:
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CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at 0x%X\n\r",LR);
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break;
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case 7:
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CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at 0x%X\n\r",LR);
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break;
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default:
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CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at 0x%X\n\r",LR);
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break;
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}
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SerialPortWrite ((UINT8 *) Buffer, CharCount);
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while(1);
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}
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