mirror of https://github.com/acidanthera/audk.git
612 lines
16 KiB
ArmAsm
612 lines
16 KiB
ArmAsm
#------------------------------------------------------------------------------
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#
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# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php.
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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# Abstract:
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#
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# Provide FSP API entry points.
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#
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#------------------------------------------------------------------------------
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#.INCLUDE "UcodeLoad.inc"
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#
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# Following are fixed PCDs
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#
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.equ MSR_IA32_PLATFORM_ID, 0x000000017
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.equ MSR_IA32_BIOS_UPDT_TRIG, 0x000000079
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.equ MSR_IA32_BIOS_SIGN_ID, 0x00000008b
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ASM_GLOBAL ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamBase)
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ASM_GLOBAL ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamSize)
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ASM_GLOBAL ASM_PFX(_gPcd_FixedAtBuild_PcdFspTemporaryRamSize)
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ASM_GLOBAL ASM_PFX(_gPcd_FixedAtBuild_PcdFspAreaSize)
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#
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# Following functions will be provided in C
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#
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#EXTERNDEF SecStartup:PROC
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#EXTERNDEF FspApiCallingCheck:PROC
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#
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# Following functions will be provided in PlatformSecLib
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#
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#EXTERNDEF GetFspBaseAddress:PROC
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#EXTERNDEF GetBootFirmwareVolumeOffset:PROC
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#EXTERNDEF PlatformTempRamInit:PROC
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#EXTERNDEF Pei2LoaderSwitchStack:PROC
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#EXTERN FspSelfCheck(FspSelfCheckDflt):PROC
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#EXTERN PlatformBasicInit(PlatformBasicInitDflt):PROC
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#
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# Define the data length that we saved on the stack top
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#
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.equ DATA_LEN_OF_PER0, 0x018
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.equ DATA_LEN_OF_MCUD, 0x018
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.equ DATA_LEN_AT_STACK_TOP, (DATA_LEN_OF_PER0 + DATA_LEN_OF_MCUD + 4)
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#
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# Define SSE macros
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#
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.macro ENABLE_SSE
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movl %cr4, %eax
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orl $0x00000600,%eax # Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
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movl %eax,%cr4
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.endm
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.macro SAVE_REGS
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movd %ebp, %xmm7
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pshufd $0x93, %xmm7, %xmm7
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movd %ebx, %xmm6
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por %xmm6, %xmm7
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pshufd $0x93, %xmm7, %xmm7
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movd %esi,%xmm6
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por %xmm6, %xmm7
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pshufd $0x93, %xmm7, %xmm7
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movd %edi, %xmm6
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por %xmm6, %xmm7
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movd %esp, %xmm6
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.endm
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.macro LOAD_REGS
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movd %xmm6, %esp
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movd %xmm7, %edi
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pshufd $0x39,%xmm7, %xmm7
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movd %xmm7, %esi
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pshufd $0x39,%xmm7, %xmm7
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movd %xmm7, %ebx
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pshufd $0x39, %xmm7, %xmm7
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movd %xmm7, %ebp
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.endm
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.macro LOAD_ESP
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movd %xmm6, %esp
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.endm
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#------------------------------------------------------------------------------
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ASM_GLOBAL ASM_PFX(FspSelfCheckDflt)
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ASM_PFX(FspSelfCheckDflt):
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# Inputs:
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# eax -> Return address
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# Outputs:
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# eax -> 0 - Successful, Non-zero - Failed.
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# Register Usage:
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# eax is cleared and ebp is used for return address.
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# All others reserved.
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# Save return address to EBP
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movl %eax, %ebp
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xorl %eax, %eax
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exit:
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jmp *%ebp
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#FspSelfCheckDflt ENDP
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#------------------------------------------------------------------------------
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ASM_GLOBAL ASM_PFX(PlatformBasicInitDflt)
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ASM_PFX(PlatformBasicInitDflt):
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# Inputs:
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# eax -> Return address
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# Outputs:
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# eax -> 0 - Successful, Non-zero - Failed.
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# Register Usage:
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# eax is cleared and ebp is used for return address.
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# All others reserved.
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# Save return address to EBP
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movl %eax, %ebp
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xorl %eax, %eax
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exit2:
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jmp *%ebp
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#PlatformBasicInitDflt ENDP
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#------------------------------------------------------------------------------
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ASM_GLOBAL ASM_PFX(LoadUcode)
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ASM_PFX(LoadUcode):
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# Inputs:
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# esp -> LOAD_UCODE_PARAMS pointer
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# Register Usage:
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# esp Preserved
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# All others destroyed
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# Assumptions:
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# No memory available, stack is hard-coded and used for return address
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# Executed by SBSP and NBSP
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# Beginning of microcode update region starts on paragraph boundary
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#
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#
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# Save return address to EBP
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movl %eax, %ebp
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cmpl $0, %esp
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jz paramerror
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movl (%esp), %eax #dword ptr [] Parameter pointer
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cmpl $0, %eax
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jz paramerror
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movl %eax, %esp
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movl (%esp), %esi #LOAD_UCODE_PARAMS.ucode_code_addr
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cmpl $0, %esi
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jnz L0
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paramerror:
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movl $0x080000002, %eax
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jmp exit4
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movl (%esp), %esi #.LOAD_UCODE_PARAMS.ucode_code_addr
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check_main_header:
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# Get processor signature and platform ID from the installed processor
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# and save into registers for later use
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# ebx = processor signature
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# edx = platform ID
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movl $1, %eax
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cpuid
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movl %eax, %ebx
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movl MSR_IA32_PLATFORM_ID, %ecx
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rdmsr
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movl %edx, %ecx
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#--------------------------------------------------------------------------------------------------------------------
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shrl $18, %ecx #($50-$32)
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andl $0x7, %ecx
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movl $1, %edx
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shll %cl,%edx
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# Current register usage
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# esp -> stack with paramters
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# esi -> microcode update to check
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# ebx = processor signature
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# edx = platform ID
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# Check for valid microcode header
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# Minimal test checking for header version and loader version as 1
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movl $1, %eax
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cmpl %eax, (%esi) #.ucode_hdr.version
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jne advance_fixed_size
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cmpl %eax, 0x18(%esi) #.ucode_hdr.loader
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jne advance_fixed_size
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# Check if signature and plaform ID match
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#--------------------------------------------------------------------------------------------------------------------------
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cmpl 0x10(%esi), %ebx #(%esi).ucode_hdr.processor
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jne L0
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testl 0x1c(%esi) , %edx #(%esi).ucode_hdr.flags
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jnz load_check # Jif signature and platform ID match
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L0:
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# Check if extended header exists
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# First check if total_size and data_size are valid
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xorl %eax, %eax
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cmpl %eax,0x24(%esi) #(%esi).ucode_hdr.total_size
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je next_microcode
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cmpl %eax,0x20(%esi) #(%esi) .ucode_hdr.data_size
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je next_microcode
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# Then verify total size - sizeof header > data size
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movl 0x24(%esi), %ecx #(%esi).ucode_hdr.total_size
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subl $0x30, %ecx #sizeof ucode_hdr = 48
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cmpl 0x20(%esi), %ecx #(%esi).ucode_hdr.data_size
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jz load_check
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jb next_microcode # Jif extended header does not exist
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# Check if total size fits in microcode region
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movl %esi , %edi
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addl 0x24(%esi), %edi # (%esi).ucode_hdr.total_size
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movl (%esp), %ecx # (%esp).LOAD_UCODE_PARAMS.ucode_code_addr
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addl 4(%esp), %ecx #.LOAD_UCODE_PARAMS.ucode_code_size
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cmpl %ecx , %edi
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xorl %eax, %eax
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ja exit4 # Jif address is outside of ucode region
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# Set edi -> extended header
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movl %esi , %edi
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addl $0x30 , %edi #sizeof ucode_hdr = 48
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addl 0x20(%esi), %edi #%esi.ucode_hdr.data_size
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# Get count of extended structures
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movl (%edi), %ecx #(%edi).ext_sig_hdr.count
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# Move pointer to first signature structure
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addl $0x20, %edi # sizeof ext_sig_hdr = 20
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check_ext_sig:
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# Check if extended signature and platform ID match
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cmpl %ebx, (%edi) #[edi].ext_sig.processor
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jne L1
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test %edx, 4(%edi) #[edi].ext_sig.flags
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jnz load_check # Jif signature and platform ID match
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L9:
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# Check if any more extended signatures exist
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addl $0xc, %edi #sizeof ext_sig = 12
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loop check_ext_sig
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next_microcode:
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# Advance just after end of this microcode
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xorl %eax, %eax
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cmpl %eax, 0x24(%esi) #(%esi).ucode_hdr.total_size
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je L2
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add 0x24(%esi) , %esi #(%esi).ucode_hdr.total_size
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jmp check_address
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L10:
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addl $0x800, %esi
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jmp check_address
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advance_fixed_size:
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# Advance by 4X dwords
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addl $0x400, %esi
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check_address:
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# Is valid Microcode start point ?
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cmp $0x0ffffffff , %esi
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jz done
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# Address >= microcode region address + microcode region size?
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movl (%esp), %eax #(%esp).LOAD_UCODE_PARAMS.ucode_code_addr
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addl 4(%esp), %eax #(%esp).LOAD_UCODE_PARAMS.ucode_code_size
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cmpl %eax, %esi
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jae done #Jif address is outside of ucode region
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jmp check_main_header
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load_check:
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# Get the revision of the current microcode update loaded
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movl MSR_IA32_BIOS_SIGN_ID, %ecx
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xorl %eax, %eax # Clear EAX
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xorl %edx, %edx # Clear EDX
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wrmsr # Load 0 to MSR at 8Bh
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movl $1, %eax
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cpuid
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movl MSR_IA32_BIOS_SIGN_ID, %ecx
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rdmsr # Get current microcode signature
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# Verify this microcode update is not already loaded
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cmpl %edx, 4(%esi) #(%esi).ucode_hdr.revision
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je continue
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load_microcode:
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# EAX contains the linear address of the start of the Update Data
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# EDX contains zero
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# ECX contains 79h (IA32_BIOS_UPDT_TRIG)
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# Start microcode load with wrmsr
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mov %esi, %eax
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add $0x30, %eax #sizeof ucode_hdr = 48
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xorl %edx, %edx
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mov MSR_IA32_BIOS_UPDT_TRIG,%ecx
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wrmsr
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mov $1, %eax
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cpuid
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continue:
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jmp next_microcode
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done:
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mov $1, %eax
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cpuid
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mov MSR_IA32_BIOS_SIGN_ID, %ecx
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rdmsr # Get current microcode signature
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xorl %eax, %eax
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cmp $0 , %edx
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jnz exit4
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mov $0x08000000E, %eax
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exit4:
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jmp *%ebp
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#LoadUcode ENDP
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#----------------------------------------------------------------------------
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# TempRamInit API
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#
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# This FSP API will load the microcode update, enable code caching for the
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# region specified by the boot loader and also setup a temporary stack to be
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# used till main memory is initialized.
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#
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#----------------------------------------------------------------------------
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ASM_GLOBAL ASM_PFX(TempRamInitApi)
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ASM_PFX(TempRamInitApi):
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#
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# Ensure SSE is enabled
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#
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ENABLE_SSE
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#
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# Save EBP, EBX, ESI, EDI & ESP in XMM7 & XMM6
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#
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SAVE_REGS
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#
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# Save timestamp into XMM4 & XMM5
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#
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rdtsc
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movd %edx, %xmm4
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movd %eax, %xmm5
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#
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# CPUID/DeviceID check
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#
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movl L11, %eax
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jmp ASM_PFX(FspSelfCheck) # Note: ESP can not be changed.
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L11:
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cmpl $0, %eax
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jnz NemInitExit
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#
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# Platform Basic Init.
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#
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movl L1, %eax
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jmp ASM_PFX(PlatformBasicInitDflt)
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L1:
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cmp $0, %eax
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jnz NemInitExit
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#
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# Load microcode
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#
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movl L2, %eax
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addl $4, %esp
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jmp LoadUcode
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L2:
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LOAD_ESP
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cmpl $0, %eax
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jnz NemInitExit
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#
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# Call platform NEM init
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#-------------------------------------------------------------------------------------------------------------------------
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movl L3, %eax
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addl $4, %esp
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jmp ASM_PFX(PlatformTempRamInit)
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L3:
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subl $4, %esp
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cmpl $0, %eax
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jnz NemInitExit
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#
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# Save parameter pointer in edx
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#
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movl 4(%esp), %edx
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#
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# Enable FSP STACK
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#
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movl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamBase), %esp
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addl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamSize), %esp
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pushl $DATA_LEN_OF_MCUD # Size of the data region
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pushl 0x4455434D # Signature of the data region 'MCUD'
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pushl 12(%edx) # Code size
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pushl 8(%edx) # Code base
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cmpl $0, %edx # Is parameter pointer valid ?
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jz InvalidMicrocodeRegion
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pushl 4(%edx) # Microcode size
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pushl (%edx) # Microcode base
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jmp L4
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InvalidMicrocodeRegion:
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pushl $0 # Microcode size
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pushl $0 # Microcode base
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L4:
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#
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# Save API entry/exit timestamp into stack
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#
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pushl DATA_LEN_OF_PER0 # Size of the data region
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pushl 0x30524550 # Signature of the data region 'PER0'
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movd %xmm4, %eax
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pushl %eax
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movd %xmm5, %eax
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pushl %eax
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rdtsc
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pushl %edx
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pushl %eax
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#
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# Terminator for the data on stack
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#
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pushl $0
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#
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# Set ECX/EDX to the bootloader temporary memory range
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#
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movl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamBase), %ecx
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movl %ecx, %edx
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addl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamSize), %edx
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subl ASM_PFX(_gPcd_FixedAtBuild_PcdFspTemporaryRamSize), %edx
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xorl %eax, %eax
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NemInitExit:
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#
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# Load EBP, EBX, ESI, EDI & ESP from XMM7 & XMM6
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#
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LOAD_REGS
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ret
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#TempRamInitApi ENDP
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#----------------------------------------------------------------------------
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# FspInit API
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#
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# This FSP API will perform the processor and chipset initialization.
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# This API will not return. Instead, it transfers the control to the
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# ContinuationFunc provided in the parameter.
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#
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#----------------------------------------------------------------------------
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ASM_GLOBAL ASM_PFX(FspInitApi)
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ASM_PFX(FspInitApi):
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#
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# Stack must be ready
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#
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pushl $0x087654321
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pop %eax
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cmpl $0x087654321, %eax
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jz L5
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movl $0x080000003, %eax
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jmp exit3
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L5:
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#
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# Additional check
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#
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pusha
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pushl $1
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call ASM_PFX(FspApiCallingCheck)
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addl $4, %esp
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movl %eax, 28(%esp)
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popa
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cmpl $0 , %eax
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jz L6
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jmp exit3
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L6:
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#
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# Save the Platform Data Pointer in EDI
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#
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movl 4(%esp), %edi
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#
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# Store the address in FSP which will return control to the BL
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#
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pushl $exit3
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#
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# Create a Task Frame in the stack for the Boot Loader
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#
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pushfl
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pushfl # 2 pushf for 4 byte alignment
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cli
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pushal
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# Reserve 8 bytes for IDT save/restore
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pushl $0
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pushl $0
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sidt (%esp)
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#
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# Setup new FSP stack
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#
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movl %esp, %eax
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movl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamBase), %esp
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addl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamSize) , %esp
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subl DATA_LEN_AT_STACK_TOP, %esp
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addl $0x0FFFFFFC0, %esp
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#
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# Save the bootloader's stack pointer
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#
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pushl %eax
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#
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# Pass entry point of the PEI core
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#
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call ASM_PFX(GetFspBaseAddress)
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movl %eax, %edi
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addl ASM_PFX(_gPcd_FixedAtBuild_PcdFspAreaSize), %edi
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subl $0x20, %edi
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addl %ds:(%edi), %eax
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pushl %eax
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#
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# Pass BFV into the PEI Core
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# It uses relative address to calucate the actual boot FV base
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# For FSP impleantion with single FV, PcdFlashFvRecoveryBase and
|
|
# PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs,
|
|
# they are different. The code below can handle both cases.
|
|
#
|
|
call ASM_PFX(GetFspBaseAddress)
|
|
movl %eax , %edi
|
|
call ASM_PFX(GetBootFirmwareVolumeOffset)
|
|
addl %edi ,%eax
|
|
pushl %eax
|
|
|
|
#
|
|
# Pass stack base and size into the PEI Core
|
|
#
|
|
movl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamBase), %eax
|
|
addl ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamSize), %eax
|
|
subl ASM_PFX(_gPcd_FixedAtBuild_PcdFspTemporaryRamSize), %eax
|
|
pushl %eax
|
|
pushl ASM_PFX(_gPcd_FixedAtBuild_PcdFspTemporaryRamSize)
|
|
|
|
#
|
|
# Pass Control into the PEI Core
|
|
#
|
|
call ASM_PFX(SecStartup)
|
|
|
|
exit3:
|
|
ret
|
|
|
|
# FspInitApi ENDP
|
|
|
|
#----------------------------------------------------------------------------
|
|
# NotifyPhase API
|
|
#
|
|
# This FSP API will notify the FSP about the different phases in the boot
|
|
# process
|
|
#
|
|
#----------------------------------------------------------------------------
|
|
ASM_GLOBAL ASM_PFX(NotifyPhaseApi)
|
|
ASM_PFX(NotifyPhaseApi):
|
|
#
|
|
# Stack must be ready
|
|
#
|
|
pushl $0x0087654321
|
|
pop %eax
|
|
cmpl $0x087654321, %eax
|
|
jz L7
|
|
movl $0x080000003, %eax
|
|
jmp err_exit
|
|
|
|
L7:
|
|
#
|
|
# Verify the calling condition
|
|
#
|
|
pusha
|
|
pushl $2
|
|
call ASM_PFX(FspApiCallingCheck)
|
|
add $4, %esp
|
|
mov %eax, 28(%esp)
|
|
popa
|
|
|
|
cmpl $0, %eax
|
|
jz L8
|
|
|
|
#
|
|
# Error return
|
|
#
|
|
err_exit:
|
|
ret
|
|
|
|
L8:
|
|
jmp ASM_PFX(Pei2LoaderSwitchStack)
|
|
|
|
#NotifyPhaseApi ENDP
|
|
|
|
|
|
#END
|