mirror of https://github.com/acidanthera/audk.git
329 lines
14 KiB
Plaintext
329 lines
14 KiB
Plaintext
#/** @file
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# ARM processor package.
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#
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# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
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# Copyright (c) 2011 - 2017, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#**/
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[Defines]
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DEC_SPECIFICATION = 0x00010005
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PACKAGE_NAME = ArmPkg
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PACKAGE_GUID = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F
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PACKAGE_VERSION = 0.1
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################################################################################
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#
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# Include Section - list of Include Paths that are provided by this package.
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# Comments are used for Keywords and Module Types.
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#
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# Supported Module Types:
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# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
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#
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################################################################################
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[Includes.common]
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Include # Root include for the package
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[LibraryClasses.common]
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ArmLib|Include/Library/ArmLib.h
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ArmMmuLib|Include/Library/ArmMmuLib.h
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SemihostLib|Include/Library/Semihosting.h
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UncachedMemoryAllocationLib|Include/Library/UncachedMemoryAllocationLib.h
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DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
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ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
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ArmGicArchLib|Include/Library/ArmGicArchLib.h
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[Guids.common]
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gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }
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## ARM MPCore table
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# Include/Guid/ArmMpCoreInfo.h
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gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }
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[Ppis]
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## Include/Ppi/ArmMpCoreInfo.h
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gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }
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[Protocols.common]
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gVirtualUncachedPagesProtocolGuid = { 0xAD651C7D, 0x3C22, 0x4DBF, { 0x92, 0xe8, 0x38, 0xa7, 0xcd, 0xae, 0x87, 0xb2 } }
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[PcdsFeatureFlag.common]
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gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001
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# On ARM Architecture with the Security Extension, the address for the
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# Vector Table can be mapped anywhere in the memory map. It means we can
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# point the Exception Vector Table to its location in CpuDxe.
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# By default we copy the Vector Table at PcdGet64(PcdCpuVectorBaseAddress)
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gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022
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# Set this PCD to TRUE if the Exception Vector is changed to add debugger support before
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# it has been configured by the CPU DXE
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gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032
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# Define if the spin-table mechanism is used by the secondary cores when booting
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# Linux (instead of PSCI)
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gArmTokenSpaceGuid.PcdArmLinuxSpinTable|FALSE|BOOLEAN|0x00000033
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# Define if the GICv3 controller should use the GICv2 legacy
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gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042
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[PcdsFeatureFlag.ARM]
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# Whether to map normal memory as non-shareable. FALSE is the safe choice, but
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# TRUE may be appropriate to fix performance problems if you don't care about
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# hardware coherency (i.e., no virtualization or cache coherent DMA)
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gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043
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[PcdsFixedAtBuild.common]
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gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
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# This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.
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# Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
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gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024
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gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000080000000|UINT64|0x00000002
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# This PCD will free the unallocated buffers if their size reach this threshold.
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# We set the default value to 512MB.
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gArmTokenSpaceGuid.PcdArmFreeUncachedMemorySizeThreshold|0x20000000|UINT64|0x00000003
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gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004
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gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005
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#
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# ARM Secure Firmware PCDs
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#
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gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015
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gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016
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gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F
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gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030
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#
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# ARM Hypervisor Firmware PCDs
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#
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gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A
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gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B
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gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C
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gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D
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# Use ClusterId + CoreId to identify the PrimaryCore
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gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031
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# The Primary Core is ClusterId[0] & CoreId[0]
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gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
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#
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# ARM L2x0 PCDs
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#
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gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B
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#
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# BdsLib
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#
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# The compressed Linux kernel is expected to be under 128MB from the beginning of the System Memory
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gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x08000000|UINT32|0x0000001F
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# Maximum file size for TFTP servers that do not support 'tsize' extension
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gArmTokenSpaceGuid.PcdMaxTftpFileSize|0x01000000|UINT32|0x00000000
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#
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# ARM Normal (or Non Secure) Firmware PCDs
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#
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gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C
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gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E
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#
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# Value to add to a host address to obtain a device address, using
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# unsigned 64-bit integer arithmetic on both ARM and AArch64. This
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# means we can rely on truncation on overflow to specify negative
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# offsets.
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#
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gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044
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[PcdsFixedAtBuild.common, PcdsPatchableInModule.common]
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gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B
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gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D
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[PcdsFixedAtBuild.ARM]
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#
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# ARM Security Extension
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#
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# Secure Configuration Register
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# - BIT0 : NS - Non Secure bit
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# - BIT1 : IRQ Handler
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# - BIT2 : FIQ Handler
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# - BIT3 : EA - External Abort
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# - BIT4 : FW - F bit writable
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# - BIT5 : AW - A bit writable
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# - BIT6 : nET - Not Early Termination
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# - BIT7 : SCD - Secure Monitor Call Disable
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# - BIT8 : HCE - Hyp Call enable
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# - BIT9 : SIF - Secure Instruction Fetch
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# 0x31 = NS | EA | FW
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gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038
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# By default we do not do a transition to non-secure mode
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gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E
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# The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory
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gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020
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# If the fixed FDT address is not available, then it should be loaded below the kernel.
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# The recommendation from the Linux kernel is to have the FDT below 16KB.
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# (see the kernel doc: Documentation/arm/Booting)
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gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x4000|UINT32|0x00000023
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# The FDT blob must be loaded at a 64bit aligned address.
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gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x8|UINT32|0x00000026
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# Non Secure Access Control Register
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# - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality
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# - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31
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# - BIT11 : cp11 - Non-secure access to coprocessor 11 enable
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# - BIT10 : cp10 - Non-secure access to coprocessor 10 enable
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# 0xC00 = cp10 | cp11
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gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039
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[PcdsFixedAtBuild.AARCH64]
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#
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# AArch64 Security Extension
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#
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# Secure Configuration Register
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# - BIT0 : NS - Non Secure bit
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# - BIT1 : IRQ Handler
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# - BIT2 : FIQ Handler
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# - BIT3 : EA - External Abort
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# - BIT4 : FW - F bit writable
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# - BIT5 : AW - A bit writable
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# - BIT6 : nET - Not Early Termination
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# - BIT7 : SCD - Secure Monitor Call Disable
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# - BIT8 : HCE - Hyp Call enable
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# - BIT9 : SIF - Secure Instruction Fetch
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# - BIT10: RW - Register width control for lower exception levels
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# - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer
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# - BIT12: TWI - Trap WFI
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# - BIT13: TWE - Trap WFE
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# 0x501 = NS | HCE | RW
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gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038
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# By default we do transition to EL2 non-secure mode with Stack for EL2.
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# Mode Description Bits
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# NS EL2 SP2 all interrupts disabled = 0x3c9
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# NS EL1 SP1 all interrupts disabled = 0x3c5
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# Other modes include using SP0 or switching to Aarch32, but these are
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# not currently supported.
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gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E
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# If the fixed FDT address is not available, then it should be loaded above the kernel.
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# The recommendation from the AArch64 Linux kernel is to have the FDT below 512MB.
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# (see the kernel doc: Documentation/arm64/booting.txt)
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gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x20000000|UINT32|0x00000023
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# The FDT blob must be loaded at a 2MB aligned address.
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gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x00200000|UINT32|0x00000026
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#
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# These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be
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# redefined when using UEFI in a context of virtual machine.
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#
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[PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]
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# System Memory (DRAM): These PCDs define the region of in-built system memory
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# Some platforms can get DRAM extensions, these additional regions will be declared
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# to UEFI by ArmPlatformLib
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gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029
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gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A
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[PcdsFixedAtBuild.common, PcdsDynamic.common]
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#
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# ARM Architectural Timer
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#
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gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034
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# ARM Architectural Timer Interrupt(GIC PPI) numbers
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gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035
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gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036
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gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040
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gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041
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#
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# ARM Generic Watchdog
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#
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gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007
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gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008
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gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009
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#
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# ARM Generic Interrupt Controller
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#
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gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C
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# Base address for the GIC Redistributor region that contains the boot CPU
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gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E
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gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D
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gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025
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#
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# Bases, sizes and translation offsets of IO and MMIO spaces, respectively.
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# Note that "IO" is just another MMIO range that simulates IO space; there
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# are no special instructions to access it.
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#
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# The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are
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# specific to their containing address spaces. In order to get the physical
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# address for the CPU, for a given access, the respective translation value
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# has to be added.
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#
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# The translations always have to be initialized like this, using UINT64:
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#
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# UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space
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# UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space
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# UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space
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#
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# PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;
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# PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;
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# PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;
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#
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# because (a) the target address space (ie. the cpu-physical space) is
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# 64-bit, and (b) the translation values are meant as offsets for *modular*
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# arithmetic.
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#
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# Accordingly, the translation itself needs to be implemented as:
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#
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# UINT64 UntranslatedIoAddress; // input parameter
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# UINT32 UntranslatedMmio32Address; // input parameter
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# UINT64 UntranslatedMmio64Address; // input parameter
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#
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# UINT64 TranslatedIoAddress; // output parameter
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# UINT64 TranslatedMmio32Address; // output parameter
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# UINT64 TranslatedMmio64Address; // output parameter
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#
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# TranslatedIoAddress = UntranslatedIoAddress +
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# PcdPciIoTranslation;
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# TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +
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# PcdPciMmio32Translation;
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# TranslatedMmio64Address = UntranslatedMmio64Address +
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# PcdPciMmio64Translation;
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#
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# The modular arithmetic performed in UINT64 ensures that the translation
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# works correctly regardless of the relation between IoCpuBase and
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# PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and
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# PcdPciMmio64Base.
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#
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gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050
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gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051
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gArmTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000052
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gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053
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gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054
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gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000055
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gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056
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gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057
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gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000058
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#
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# Inclusive range of allowed PCI buses.
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#
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gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059
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gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A
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