mirror of https://github.com/acidanthera/audk.git
143 lines
4.4 KiB
C
143 lines
4.4 KiB
C
/** @file
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* Main file supporting the transition to PEI Core in Normal World for Versatile Express
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*
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* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#include <Library/BaseLib.h>
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#include <Library/DebugAgentLib.h>
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#include <Library/ArmLib.h>
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#include "PrePeiCore.h"
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CONST EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi = { PrePeiCoreTemporaryRamSupport };
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CONST EFI_PEI_PPI_DESCRIPTOR gCommonPpiTable[] = {
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{
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EFI_PEI_PPI_DESCRIPTOR_PPI,
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&gEfiTemporaryRamSupportPpiGuid,
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(VOID *) &mTemporaryRamSupportPpi
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}
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};
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VOID
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CreatePpiList (
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OUT UINTN *PpiListSize,
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OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
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)
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{
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EFI_PEI_PPI_DESCRIPTOR *PlatformPpiList;
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UINTN PlatformPpiListSize;
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UINTN ListBase;
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EFI_PEI_PPI_DESCRIPTOR *LastPpi;
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// Get the Platform PPIs
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PlatformPpiListSize = 0;
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ArmPlatformGetPlatformPpiList (&PlatformPpiListSize, &PlatformPpiList);
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// Copy the Common and Platform PPis in Temporary Memory
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ListBase = PcdGet64 (PcdCPUCoresStackBase);
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CopyMem ((VOID*)ListBase, gCommonPpiTable, sizeof(gCommonPpiTable));
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CopyMem ((VOID*)(ListBase + sizeof(gCommonPpiTable)), PlatformPpiList, PlatformPpiListSize);
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// Set the Terminate flag on the last PPI entry
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LastPpi = (EFI_PEI_PPI_DESCRIPTOR*)ListBase + ((sizeof(gCommonPpiTable) + PlatformPpiListSize) / sizeof(EFI_PEI_PPI_DESCRIPTOR)) - 1;
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LastPpi->Flags |= EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
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*PpiList = (EFI_PEI_PPI_DESCRIPTOR*)ListBase;
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*PpiListSize = sizeof(gCommonPpiTable) + PlatformPpiListSize;
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}
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VOID
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CEntryPoint (
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IN UINTN MpId,
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IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
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)
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{
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// Data Cache enabled on Primary core when MMU is enabled.
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ArmDisableDataCache ();
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// Invalidate Data cache
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ArmInvalidateDataCache ();
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// Invalidate instruction cache
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ArmInvalidateInstructionCache ();
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// Enable Instruction Caches on all cores.
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ArmEnableInstructionCache ();
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//
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// Note: Doesn't have to Enable CPU interface in non-secure world,
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// as Non-secure interface is already enabled in Secure world.
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//
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// Write VBAR - The Exception Vector table must be aligned to its requirement
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// Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure
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// 'Align=4K' is defined into your FDF for this module.
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ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
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ArmWriteVBar ((UINTN)PeiVectorTable);
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// Enable Floating Point
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if (FixedPcdGet32 (PcdVFPEnabled)) {
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ArmEnableVFP ();
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}
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//Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.
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// If not primary Jump to Secondary Main
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if (ArmPlatformIsPrimaryCore (MpId)) {
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// Initialize the Debug Agent for Source Level Debugging
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InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);
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SaveAndSetDebugTimerInterrupt (TRUE);
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// Initialize the platform specific controllers
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ArmPlatformInitialize (MpId);
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// Goto primary Main.
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PrimaryMain (PeiCoreEntryPoint);
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} else {
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SecondaryMain (MpId);
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}
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// PEI Core should always load and never return
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ASSERT (FALSE);
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}
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EFI_STATUS
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EFIAPI
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PrePeiCoreTemporaryRamSupport (
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IN CONST EFI_PEI_SERVICES **PeiServices,
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IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
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IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
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IN UINTN CopySize
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)
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{
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VOID *OldHeap;
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VOID *NewHeap;
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VOID *OldStack;
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VOID *NewStack;
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UINTN HeapSize;
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HeapSize = ALIGN_VALUE (CopySize / 2, CPU_STACK_ALIGNMENT);
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OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;
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NewHeap = (VOID*)((UINTN)PermanentMemoryBase + (CopySize - HeapSize));
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OldStack = (VOID*)((UINTN)TemporaryMemoryBase + HeapSize);
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NewStack = (VOID*)(UINTN)PermanentMemoryBase;
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//
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// Migrate the temporary memory stack to permanent memory stack.
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//
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CopyMem (NewStack, OldStack, CopySize - HeapSize);
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//
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// Migrate the temporary memory heap to permanent memory heap.
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//
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CopyMem (NewHeap, OldHeap, HeapSize);
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SecSwitchStack ((UINTN)NewStack - (UINTN)OldStack);
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return EFI_SUCCESS;
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}
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