mirror of https://github.com/acidanthera/audk.git
155 lines
4.0 KiB
NASM
155 lines
4.0 KiB
NASM
;------------------------------------------------------------------------------
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; @file
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; Relocate the SMBASE on a hot-added CPU when it services its first SMI.
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;
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; Copyright (c) 2020, Red Hat, Inc.
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;
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; The routine runs on the hot-added CPU in the following "big real mode",
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; 16-bit environment; per "SMI HANDLER EXECUTION ENVIRONMENT" in the Intel SDM
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; (table "Processor Register Initialization in SMM"):
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;
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; - CS selector: 0x3000 (most significant 16 bits of SMM_DEFAULT_SMBASE).
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;
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; - CS limit: 0xFFFF_FFFF.
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;
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; - CS base: SMM_DEFAULT_SMBASE (0x3_0000).
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;
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; - IP: SMM_HANDLER_OFFSET (0x8000).
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;
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; - ES, SS, DS, FS, GS selectors: 0.
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;
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; - ES, SS, DS, FS, GS limits: 0xFFFF_FFFF.
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;
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; - ES, SS, DS, FS, GS bases: 0.
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;
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; - Operand-size and address-size override prefixes can be used to access the
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; address space beyond 1MB.
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;------------------------------------------------------------------------------
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SECTION .data
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BITS 16
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;
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; Bring in SMM_DEFAULT_SMBASE from
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; "MdePkg/Include/Register/Intel/SmramSaveStateMap.h".
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;
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SMM_DEFAULT_SMBASE: equ 0x3_0000
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;
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; Field offsets in FIRST_SMI_HANDLER_CONTEXT, which resides at
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; SMM_DEFAULT_SMBASE.
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;
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ApicIdGate: equ 0 ; UINT64
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NewSmbase: equ 8 ; UINT32
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AboutToLeaveSmm: equ 12 ; UINT8
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;
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; SMRAM Save State Map field offsets, per the AMD (not Intel) layout that QEMU
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; implements. Relative to SMM_DEFAULT_SMBASE.
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;
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SaveStateRevId: equ 0xFEFC ; UINT32
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SaveStateSmbase: equ 0xFEF8 ; UINT32
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SaveStateSmbase64: equ 0xFF00 ; UINT32
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;
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; CPUID constants, from "MdePkg/Include/Register/Intel/Cpuid.h".
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;
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CPUID_SIGNATURE: equ 0x00
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CPUID_EXTENDED_TOPOLOGY: equ 0x0B
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CPUID_VERSION_INFO: equ 0x01
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GLOBAL ASM_PFX (mFirstSmiHandler) ; UINT8[]
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GLOBAL ASM_PFX (mFirstSmiHandlerSize) ; UINT16
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ASM_PFX (mFirstSmiHandler):
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;
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; Get our own APIC ID first, so we can contend for ApicIdGate.
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;
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; This basically reimplements GetInitialApicId() from
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; "UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c".
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;
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mov eax, CPUID_SIGNATURE
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cpuid
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cmp eax, CPUID_EXTENDED_TOPOLOGY
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jb GetApicIdFromVersionInfo
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mov eax, CPUID_EXTENDED_TOPOLOGY
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mov ecx, 0
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cpuid
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test ebx, 0xFFFF
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jz GetApicIdFromVersionInfo
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;
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; EDX has the APIC ID, save it to ESI.
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;
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mov esi, edx
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jmp KnockOnGate
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GetApicIdFromVersionInfo:
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mov eax, CPUID_VERSION_INFO
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cpuid
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shr ebx, 24
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;
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; EBX has the APIC ID, save it to ESI.
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;
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mov esi, ebx
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KnockOnGate:
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;
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; See if ApicIdGate shows our own APIC ID. If so, swap it to MAX_UINT64
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; (close the gate), and advance. Otherwise, keep knocking.
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;
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; InterlockedCompareExchange64():
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; - Value := &FIRST_SMI_HANDLER_CONTEXT.ApicIdGate
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; - CompareValue (EDX:EAX) := APIC ID (from ESI)
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; - ExchangeValue (ECX:EBX) := MAX_UINT64
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;
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mov edx, 0
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mov eax, esi
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mov ecx, 0xFFFF_FFFF
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mov ebx, 0xFFFF_FFFF
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lock cmpxchg8b [ds : dword (SMM_DEFAULT_SMBASE + ApicIdGate)]
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jz ApicIdMatch
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pause
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jmp KnockOnGate
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ApicIdMatch:
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;
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; Update the SMBASE field in the SMRAM Save State Map.
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;
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; First, calculate the address of the SMBASE field, based on the SMM Revision
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; ID; store the result in EBX.
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;
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mov eax, dword [ds : dword (SMM_DEFAULT_SMBASE + SaveStateRevId)]
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test eax, 0xFFFF
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jz LegacySaveStateMap
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mov ebx, SMM_DEFAULT_SMBASE + SaveStateSmbase64
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jmp UpdateSmbase
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LegacySaveStateMap:
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mov ebx, SMM_DEFAULT_SMBASE + SaveStateSmbase
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UpdateSmbase:
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;
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; Load the new SMBASE value into EAX.
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;
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mov eax, dword [ds : dword (SMM_DEFAULT_SMBASE + NewSmbase)]
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;
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; Save it to the SMBASE field whose address we calculated in EBX.
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;
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mov dword [ds : dword ebx], eax
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;
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; Set AboutToLeaveSmm.
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;
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mov byte [ds : dword (SMM_DEFAULT_SMBASE + AboutToLeaveSmm)], 1
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;
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; We're done; leave SMM and continue to the pen.
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;
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rsm
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ASM_PFX (mFirstSmiHandlerSize):
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dw $ - ASM_PFX (mFirstSmiHandler)
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