mirror of https://github.com/acidanthera/audk.git
139 lines
4.6 KiB
C
139 lines
4.6 KiB
C
/*++
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Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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Platform.h
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Abstract:
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Pinetrail platform specific information.
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**/
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#ifndef _PLATFORM_H
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#define _PLATFORM_H
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#include "ChipsetAccess.h"
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#include "PlatformBaseAddresses.h"
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//
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// Number of P & T states supported.
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//
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#define NPTM_P_STATES_SUPPORTED 16
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#define NPTM_T_STATES_SUPPORTED 8
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//
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// I/O APIC IDs, the code uses math to generate the numbers
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// instead of using these defines.
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//
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#define ICH_IOAPIC (1 << 0)
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#define ICH_IOAPIC_ID 0x08
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//
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// Possible SMBus addresses that will be present.
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//
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#define SMBUS_ADDR_CH_A_1 0xA0
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#define SMBUS_ADDR_CH_A_2 0xA2
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#define SMBUS_ADDR_CH_B_1 0xA4
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#define SMBUS_ADDR_CH_B_2 0xA6
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#define SMBUS_ADDR_CH_C_1 0xA8
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#define SMBUS_ADDR_CH_C_2 0xAA
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#define SMBUS_ADDR_CH_D_1 0xAC
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#define SMBUS_ADDR_CH_D_2 0xAE
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#define SMBUS_ADDR_HOST_CLK_BUFFER 0xDC
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#define SMBUS_ADDR_ICH_SLAVE 0x44
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#define SMBUS_ADDR_HECETA 0x5C
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#define SMBUS_ADDR_SMBARP 0xC2
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#define SMBUS_ADDR_82573E 0xC6
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#define SMBUS_ADDR_CLKCHIP 0xD2
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#define SMBUS_ADDR_BRD_REV 0x4E
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#define SMBUS_ADDR_DB803 0x82
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//
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// SMBus addresses that used on this platform.
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//
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#define PLATFORM_SMBUS_RSVD_ADDRESSES { \
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SMBUS_ADDR_CH_A_1, \
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SMBUS_ADDR_CH_A_2, \
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SMBUS_ADDR_HOST_CLK_BUFFER, \
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SMBUS_ADDR_ICH_SLAVE, \
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SMBUS_ADDR_SMBARP, \
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SMBUS_ADDR_CLKCHIP, \
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SMBUS_ADDR_BRD_REV, \
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SMBUS_ADDR_DB803 \
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}
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//
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// Count of addresses present in PLATFORM_SMBUS_RSVD_ADDRESSES.
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//
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#define PLATFORM_NUM_SMBUS_RSVD_ADDRESSES 8
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//
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// CMOS usage
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//
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#define CMOS_CPU_BSP_SELECT 0x10
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#define CMOS_CPU_UP_MODE 0x11
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#define CMOS_CPU_RATIO_OFFSET 0x12
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#define CMOS_CPU_CORE_HT_OFFSET 0x13
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#define CMOS_EFI_DEBUG 0x14
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#define CMOS_CPU_BIST_OFFSET 0x15
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#define CMOS_CPU_VMX_OFFSET 0x16
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#define CMOS_ICH_PORT80_OFFSET 0x17
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#define CMOS_PLATFORM_DESIGNATOR 0x18 // Second bank CMOS location of Platform ID.
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#define CMOS_VALIDATION_TEST_BYTE 0x19 // BIT0 - Validation mailbox for UPonDP.
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#define CMOS_SERIAL_BAUD_RATE 0x1A // 0=115200; 1=57600; 2=38400; 3=19200; 4=9600
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#define CMOS_DCU_MODE_OFFSET 0x1B
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#define CMOS_VR11_SET_OFFSET 0x1C
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#define CMOS_SBSP_TO_AP_COMM 0x20 // SEC code use ONLY!!!
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#define CMOS_RESET_TYPE_BY_OS 0x52
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#define TCG_CMOS_MOR_AREA_OFFSET 0x65 // Also Change in Universal\Security\Tpm\PhysicalPresence\Dxe\PhysicalPresence.c &
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#define CMOS_S4_WAKEUP_FLAG_ADDRESS 0x6E
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#define ACPI_TPM_REQUEST 0x75
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#define ACPI_TPM_LAST_REQUEST 0x76
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#define CMOS_BOOT_FLAG_ADDRESS 0x7E
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//
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// GPIO Index Data Structure.
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//
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typedef struct {
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UINT8 Register;
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UINT32 Value;
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} ICH_GPIO_DEV;
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//
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// CPU Equates
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//
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#define MAX_THREAD 2
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#define MAX_CORE 1
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#define MAX_DIE 2
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#define MAX_CPU_SOCKET 1
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#define MAX_CPU_NUM (MAX_THREAD * MAX_CORE * MAX_DIE * MAX_CPU_SOCKET)
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#define MEM64_LEN 0x00100000000
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#define RES_MEM64_36_BASE 0x01000000000 - MEM64_LEN // 2^36
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#define RES_MEM64_36_LIMIT 0x01000000000 - 1 // 2^36
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#define RES_MEM64_39_BASE 0x08000000000 - MEM64_LEN // 2^39
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#define RES_MEM64_39_LIMIT 0x08000000000 - 1 // 2^39
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#define RES_MEM64_40_BASE 0x10000000000 - MEM64_LEN // 2^40
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#define RES_MEM64_40_LIMIT 0x10000000000 - 1 // 2^40
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#define PLATFORM_MAX_BUS_NUM 0x3f
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#define V_DEFAULT_SUBSYSTEM_DEVICE_ID 0x574d
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#define V_DEFAULT_SUBSYSTEM_DEVICE_ID_KT 0x544b
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#define V_DEFAULT_SUBSYSTEM_VENDOR_ID 0x8086
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#endif
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