mirror of https://github.com/acidanthera/audk.git
167 lines
5.3 KiB
C
167 lines
5.3 KiB
C
/************************************************************************
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*
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* Copyright (c) 2013-2015 Intel Corporation.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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************************************************************************/
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#ifndef _MRC_H_
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#define _MRC_H_
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#include "core_types.h"
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// define the MRC Version
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#define MRC_VERSION 0x0112
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// architectural definitions
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#define NUM_CHANNELS 1 // number of channels
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#define NUM_RANKS 2 // number of ranks per channel
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#define NUM_BYTE_LANES 4 // number of byte lanes per channel
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// software limitations
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#define MAX_CHANNELS 1
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#define MAX_RANKS 2
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#define MAX_BYTE_LANES 4
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// only to mock MrcWrapper
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#define MAX_SOCKETS 1
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#define MAX_SIDES 1
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#define MAX_ROWS (MAX_SIDES * MAX_SOCKETS)
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// end
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// Specify DRAM of nenory channel width
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enum {
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x8, // DRAM width
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x16, // DRAM width & Channel Width
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x32 // Channel Width
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};
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// Specify DRAM speed
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enum {
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DDRFREQ_800,
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DDRFREQ_1066
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};
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// Specify DRAM type
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enum {
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DDR3,
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DDR3L
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};
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// Delay configuration for individual signals
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// Vref setting
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// Scrambler seed
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typedef struct MrcTimings_s
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{
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uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
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uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
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uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
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uint32_t wdq [NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
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uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
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uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
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uint32_t wcmd[NUM_CHANNELS];
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uint32_t scrambler_seed;
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uint8_t ddr_speed; // need to save for the case of frequency change
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} MrcTimings_t;
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// DENSITY: 0=512Mb, 1=Gb, 2=2Gb, 3=4Gb
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// tCL is DRAM CAS Latency in clocks.
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// All other timings are in picoseconds.
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// Refer to JEDEC spec (or DRAM datasheet) when changing these values.
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typedef struct DRAMParams_s {
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uint8_t DENSITY;
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uint8_t tCL; // CAS latency in clocks
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uint32_t tRAS; // ACT to PRE command period
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uint32_t tWTR; // Delay from start of internal write transaction to internal read command
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uint32_t tRRD; // ACT to ACT command period (JESD79 specific to page size 1K/2K)
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uint32_t tFAW; // Four activate window (JESD79 specific to page size 1K/2K)
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} DRAMParams_t;
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// Boot mode defined as bit mask (1<<n)
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#define bmCold 1 // full training
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#define bmFast 2 // restore timing parameters
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#define bmS3 4 // resume from S3
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#define bmWarm 8
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#define bmUnknown 0
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// MRC execution status
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#define MRC_SUCCESS 0 // initialization ok
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#define MRC_E_MEMTEST 1 // memtest failed
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//
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// Input/output/context parameters for Memory Reference Code
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//
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typedef struct MRCParams_s
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{
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//
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// Global settings
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//
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uint32_t boot_mode; // bmCold, bmFast, bmWarm, bmS3
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uint32_t uart_mmio_base; // pcie serial port base address (force 0 to disable debug)
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uint8_t dram_width; // x8, x16
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uint8_t ddr_speed; // DDRFREQ_800, DDRFREQ_1066
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uint8_t ddr_type; // DDR3, DDR3L
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uint8_t ecc_enables; // 0, 1 (memory size reduced to 7/8)
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uint8_t scrambling_enables; // 0, 1
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uint32_t rank_enables; // 1, 3 (1'st rank has to be populated if 2'nd rank present)
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uint32_t channel_enables; // 1 only
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uint32_t channel_width; // x16 only
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uint32_t address_mode; // 0, 1, 2 (mode 2 forced if ecc enabled)
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// memConfig_t begin
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uint8_t refresh_rate; // REFRESH_RATE : 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED
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uint8_t sr_temp_range; // SR_TEMP_RANGE : 0=normal, 1=extended, others=RESERVED
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uint8_t ron_value; // RON_VALUE : 0=34ohm, 1=40ohm, others=RESERVED (select MRS1.DIC driver impedance control)
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uint8_t rtt_nom_value; // RTT_NOM_VALUE : 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED
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uint8_t rd_odt_value; // RD_ODT_VALUE : 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED
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// memConfig_t end
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DRAMParams_t params;
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//
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// Internally used
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//
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uint32_t board_id; // internally used for board layout (use x8 or x16 memory)
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uint32_t hte_setup : 1; // when set hte reconfiguration requested
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uint32_t menu_after_mrc : 1;
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uint32_t power_down_disable :1;
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uint32_t tune_rcvn :1;
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uint32_t channel_size[NUM_CHANNELS];
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uint32_t column_bits[NUM_CHANNELS];
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uint32_t row_bits[NUM_CHANNELS];
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uint32_t mrs1; // register content saved during training
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//
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// Output
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//
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uint32_t status; // initialization result (non zero specifies error code)
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uint32_t mem_size; // total memory size in bytes (excludes ECC banks)
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MrcTimings_t timings; // training results (also used on input)
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} MRCParams_t;
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// Alternative type name for consistent naming convention
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#define MRC_PARAMS MRCParams_t
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#endif // _MRC_H_
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