mirror of https://github.com/acidanthera/audk.git
0d382976c2
System paging 5 level enabled or not can be checked via CR4.LA57, system preferred Page table Level (PcdUse5LevelPageTable) must align with previous level for 64bit long mode. This patch is to do the wise check: If cpu has already run in 64bit long mode PEI, Page table Level in DXE must align with previous level. If cpu runs in 32bit protected mode PEI, Page table Level in DXE is decided by PCD and feature capability. Cc: Dandan Bi <dandan.bi@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> |
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| .. | ||
| Arm | ||
| Ebc | ||
| Ia32 | ||
| LoongArch64 | ||
| RiscV64 | ||
| X64 | ||
| DxeIpl.h | ||
| DxeIpl.inf | ||
| DxeIpl.uni | ||
| DxeIplExtra.uni | ||
| DxeLoad.c | ||