mirror of https://github.com/acidanthera/audk.git
aad9a30144
Modify CpuPageTableLib code to enable PAE paging. In PageTableMap() API: When creating new PAE page table, after creating page table, set all MustBeZero fields of 4 PDPTE to 0. The MustBeZero fields are treated as RW and other attributes by the common map logic. So they might be set to 1. When updating exsiting PAE page table, the special steps are: 1.Prepare 4K-aligned 32bytes memory in stack for 4 temp PDPTE. 2.Copy original 4 PDPTE to the 4 temp PDPTE and set the RW, UserSupervisor to 1 and set Nx of 4 temp PDPTE to 0. 4.After updating the page table, set the MustBeZero fields of 4 temp PDPTE to 0. 5.Copy the temp PDPTE to original PDPTE. In PageTableParse() API, also create 4 temp PDPTE in stack. Copy original 4 PDPTE to the 4 temp PDPTE. Then set the RW, UserSupervisor to 1 and set Nx of 4 temp PDPTE to 0. Finally use the address of temp PDPTE as the page table address. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> |
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| .. | ||
| Application/Cpuid | ||
| CpuDxe | ||
| CpuDxeRiscV64 | ||
| CpuFeatures | ||
| CpuIo2Dxe | ||
| CpuIo2Smm | ||
| CpuIoPei | ||
| CpuMpPei | ||
| CpuS3DataDxe | ||
| CpuTimerDxeRiscV64 | ||
| Include | ||
| Library | ||
| MicrocodeMeasurementDxe | ||
| PiSmmCommunication | ||
| PiSmmCpuDxeSmm | ||
| ResetVector | ||
| SecCore | ||
| SecMigrationPei | ||
| Test | ||
| Universal/Acpi/S3Resume2Pei | ||
| UefiCpuPkg.ci.yaml | ||
| UefiCpuPkg.dec | ||
| UefiCpuPkg.dsc | ||
| UefiCpuPkg.uni | ||
| UefiCpuPkgExtra.uni | ||