mirror of https://github.com/acidanthera/audk.git
02f7fd158e
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1093 Return Stack Buffer (RSB) is used to predict the target of RET instructions. When the RSB underflows, some processors may fall back to using branch predictors. This might impact software using the retpoline mitigation strategy on those processors. This commit will add RSB stuffing logic before returning from SMM (the RSM instruction) to avoid interfering with non-SMM usage of the retpoline technique. After the stuffing, RSB entries will contain a trap like: @SpecTrap: pause lfence jmp @SpecTrap A more detailed explanation of the purpose of commit is under the 'Branch target injection mitigation' section of the below link: https://software.intel.com/security-software-guidance/insights/host-firmware-speculative-execution-side-channel-mitigation Please note that this commit requires further actions (BZ 1091) to remove the duplicated 'StuffRsb.inc' files and merge them into one under a UefiCpuPkg package-level directory (such as UefiCpuPkg/Include/). REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1091 Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com> |
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| .. | ||
| Ia32 | ||
| X64 | ||
| CpuS3.c | ||
| CpuService.c | ||
| CpuService.h | ||
| MpService.c | ||
| PiSmmCpuDxeSmm.c | ||
| PiSmmCpuDxeSmm.h | ||
| PiSmmCpuDxeSmm.inf | ||
| PiSmmCpuDxeSmm.uni | ||
| PiSmmCpuDxeSmmExtra.uni | ||
| SmmCpuMemoryManagement.c | ||
| SmmProfile.c | ||
| SmmProfile.h | ||
| SmmProfileInternal.h | ||
| SmramSaveState.c | ||
| SyncTimer.c | ||