mirror of https://github.com/acidanthera/audk.git
265 lines
7.3 KiB
C
265 lines
7.3 KiB
C
/*++
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Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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Module Name:
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Fd.h
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Abstract:
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EFI Intel82802AB/82802AC Firmware Hub.
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--*/
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//
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// Supported SPI devices
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//
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//
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// MFG and Device code
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//
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#define SST_25LF040A 0x0044BF
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#define SST_25LF040 0x0040BF
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#define SST_25LF080A 0x0080BF
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#define SST_25VF080B 0x008EBF
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#define SST_25VF016B 0x0041BF
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#define SST_25VF032B 0x004ABF
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#define PMC_25LV040 0x007E9D
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#define ATMEL_26DF041 0x00441F
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#define Atmel_AT26F004 0x00041F
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#define Atmel_AT26DF081A 0x01451F
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#define Atmel_AT25DF161 0x02461F
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#define Atmel_AT26DF161 0x00461F
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#define Atmel_AT25DF641 0x00481F
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#define Atmel_AT26DF321 0x00471F
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#define Macronix_MX25L8005 0x1420C2
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#define Macronix_MX25L1605A 0x1520C2
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#define Macronix_MX25L3205D 0x1620C2
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#define STMicro_M25PE80 0x148020
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#define Winbond_W25X40 0x1330EF
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#define Winbond_W25X80 0x1430EF
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#define Winbond_W25Q80 0x1440EF
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#define Winbond_W25X16 0x1540EF // W25Q16
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#define Winbond_W25X32 0x1630EF
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//
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// NOTE: Assuming that 8Mbit flash will only contain a 4Mbit binary.
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// Treating 4Mbit and 8Mbit devices the same.
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//
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//
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// BIOS Base Address
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//
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#define BIOS_BASE_ADDRESS_4M 0xFFF80000
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#define BIOS_BASE_ADDRESS_8M 0xFFF00000
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#define BIOS_BASE_ADDRESS_16M 0xFFE00000
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//
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// block and sector sizes
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//
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#define SECTOR_SIZE_256BYTE 0x100 // 256byte page size
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#define SECTOR_SIZE_4KB 0x1000 // 4kBytes sector size
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#define BLOCK_SIZE_32KB 0x00008000 // 32Kbytes block size
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#define MAX_FLASH_SIZE 0x00400000 // 32Mbit (Note that this can also be used for the 4Mbit & 8Mbit)
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//
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// Flash commands
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//
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#define SPI_SST25LF_COMMAND_WRITE 0x02
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#define SPI_SST25LF_COMMAND_READ 0x03
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#define SPI_SST25LF_COMMAND_ERASE 0x20
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#define SPI_SST25LF_COMMAND_WRITE_DISABLE 0x04
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#define SPI_SST25LF_COMMAND_READ_STATUS 0x05
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#define SPI_SST25LF_COMMAND_WRITE_ENABLE 0x06
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#define SPI_SST25LF_COMMAND_READ_ID 0xAB
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#define SPI_SST25LF_COMMAND_WRITE_S_EN 0x50
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#define SPI_SST25LF_COMMAND_WRITE_S 0x01
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#define SPI_PMC25LV_COMMAND_WRITE 0x02
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#define SPI_PMC25LV_COMMAND_READ 0x03
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#define SPI_PMC25LV_COMMAND_ERASE 0xD7
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#define SPI_PMC25LV_COMMAND_WRITE_DISABLE 0x04
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#define SPI_PMC25LV_COMMAND_READ_STATUS 0x05
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#define SPI_PMC25LV_COMMAND_WRITE_ENABLE 0x06
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#define SPI_PMC25LV_COMMAND_READ_ID 0xAB
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#define SPI_PMC25LV_COMMAND_WRITE_S_EN 0x06
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#define SPI_PMC25LV_COMMAND_WRITE_S 0x01
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#define SPI_AT26DF_COMMAND_WRITE 0x02
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#define SPI_AT26DF_COMMAND_READ 0x03
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#define SPI_AT26DF_COMMAND_ERASE 0x20
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#define SPI_AT26DF_COMMAND_WRITE_DISABLE 0x00
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#define SPI_AT26DF_COMMAND_READ_STATUS 0x05
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#define SPI_AT26DF_COMMAND_WRITE_ENABLE 0x00
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#define SPI_AT26DF_COMMAND_READ_ID 0x9F
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#define SPI_AT26DF_COMMAND_WRITE_S_EN 0x00
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#define SPI_AT26DF_COMMAND_WRITE_S 0x00
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#define SPI_AT26F_COMMAND_WRITE 0x02
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#define SPI_AT26F_COMMAND_READ 0x03
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#define SPI_AT26F_COMMAND_ERASE 0x20
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#define SPI_AT26F_COMMAND_WRITE_DISABLE 0x04
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#define SPI_AT26F_COMMAND_READ_STATUS 0x05
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#define SPI_AT26F_COMMAND_WRITE_ENABLE 0x06
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#define SPI_AT26F_COMMAND_JEDEC_ID 0x9F
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#define SPI_AT26F_COMMAND_WRITE_S_EN 0x00
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#define SPI_AT26F_COMMAND_WRITE_S 0x01
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#define SPI_AT26F_COMMAND_WRITE_UNPROTECT 0x39
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#define SPI_SST25VF_COMMAND_WRITE 0x02
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#define SPI_SST25VF_COMMAND_READ 0x03
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#define SPI_SST25VF_COMMAND_ERASE 0x20
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#define SPI_SST25VF_COMMAND_WRITE_DISABLE 0x04
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#define SPI_SST25VF_COMMAND_READ_STATUS 0x05
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#define SPI_SST25VF_COMMAND_WRITE_ENABLE 0x06
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#define SPI_SST25VF_COMMAND_READ_ID 0xAB
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#define SPI_SST25VF_COMMAND_JEDEC_ID 0x9F
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#define SPI_SST25VF_COMMAND_WRITE_S_EN 0x50
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#define SPI_SST25VF_COMMAND_WRITE_S 0x01
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#define SPI_STM25PE_COMMAND_WRITE 0x02
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#define SPI_STM25PE_COMMAND_READ 0x03
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#define SPI_STM25PE_COMMAND_ERASE 0xDB
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#define SPI_STM25PE_COMMAND_WRITE_DISABLE 0x04
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#define SPI_STM25PE_COMMAND_READ_STATUS 0x05
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#define SPI_STM25PE_COMMAND_WRITE_ENABLE 0x06
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#define SPI_STM25PE_COMMAND_JEDEC_ID 0x9F
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#define SPI_WinbondW25X_COMMAND_WRITE_S 0x01
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#define SPI_WinbondW25X_COMMAND_WRITE 0x02
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#define SPI_WinbondW25X_COMMAND_READ 0x03
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#define SPI_WinbondW25X_COMMAND_READ_STATUS 0x05
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#define SPI_WinbondW25X_COMMAND_ERASE_S 0x20
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#define SPI_WinbondW25X_COMMAND_WRITE_ENABLE 0x06
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#define SPI_WinbondW25X_COMMAND_JEDEC_ID 0x9F
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//
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// SPI default opcode slots
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//
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#define SPI_OPCODE_WRITE_INDEX 0
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#define SPI_OPCODE_READ_INDEX 1
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#define SPI_OPCODE_ERASE_INDEX 2
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#define SPI_OPCODE_READ_S_INDEX 3
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#define SPI_OPCODE_READ_ID_INDEX 4
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#define SPI_OPCODE_WRITE_S_INDEX 6
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#define SPI_OPCODE_WRITE_UNPROTECT_INDEX 7
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#define SPI_PREFIX_WRITE_S_EN 1
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#define SPI_PREFIX_WRITE_EN 0
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//
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// Atmel AT26F00x
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//
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#define B_AT26F_STS_REG_SPRL 0x80
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#define B_AT26F_STS_REG_SWP 0x0C
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//
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// Block lock bit definitions:
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//
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#define READ_LOCK 0x04
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#define LOCK_DOWN 0x02
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#define WRITE_LOCK 0x01
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#define FULL_ACCESS 0x00
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//
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// Function Prototypes
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//
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EFI_STATUS
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FlashGetNextBlock (
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IN UINTN* Key,
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OUT EFI_PHYSICAL_ADDRESS* BlockAddress,
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OUT UINTN* BlockSize
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);
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EFI_STATUS
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FlashGetSize (
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OUT UINTN* Size
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);
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EFI_STATUS
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FlashGetUniformBlockSize (
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OUT UINTN* Size
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);
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EFI_STATUS
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FlashEraseWithNoTopSwapping (
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IN UINT8 *BaseAddress,
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IN UINTN NumBytes
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);
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EFI_STATUS
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FlashErase (
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IN UINT8 *BaseAddress,
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IN UINTN NumBytes
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);
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EFI_STATUS
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FlashWriteWithNoTopSwapping (
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IN UINT8* DstBufferPtr,
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IN UINT8* SrcBufferPtr,
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IN UINTN NumBytes
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);
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EFI_STATUS
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FlashWrite (
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IN UINT8 *DstBufferPtr,
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IN UINT8 *SrcBufferPtr,
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IN UINTN NumBytes
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);
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EFI_STATUS
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FlashReadWithNoTopSwapping (
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IN UINT8 *BaseAddress,
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IN UINT8 *DstBufferPtr,
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IN UINTN NumBytes
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);
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EFI_STATUS
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FlashRead (
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IN UINT8 *BaseAddress,
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IN UINT8 *DstBufferPtr,
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IN UINTN NumBytes
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);
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EFI_STATUS
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FlashLockWithNoTopSwapping (
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IN UINT8* BaseAddress,
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IN UINTN NumBytes,
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IN UINT8 LockState
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);
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EFI_STATUS
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FlashLock(
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IN UINT8 *BaseAddress,
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IN UINTN NumBytes,
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IN UINT8 LockState
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);
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EFI_STATUS
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CheckIfErased(
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IN UINT8 *DstBufferPtr,
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IN UINTN NumBytes
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);
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EFI_STATUS
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CheckIfFlashIsReadyForWrite (
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IN UINT8 *DstBufferPtr,
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IN UINT8 *SrcBufferPtr,
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IN UINTN NumBytes
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);
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