mirror of https://github.com/acidanthera/audk.git
329 lines
11 KiB
C
329 lines
11 KiB
C
/** @file
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x64 Long Mode Virtual Memory Management Definitions
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References:
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1) IA-32 Intel(R) Architecture Software Developer's Manual Volume 1:Basic Architecture, Intel
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2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
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3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
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4) AMD64 Architecture Programmer's Manual Volume 2: System Programming
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Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _VIRTUAL_MEMORY_H_
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#define _VIRTUAL_MEMORY_H_
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#define SYS_CODE64_SEL 0x38
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#pragma pack(1)
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typedef union {
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struct {
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UINT32 LimitLow : 16;
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UINT32 BaseLow : 16;
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UINT32 BaseMid : 8;
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UINT32 Type : 4;
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UINT32 System : 1;
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UINT32 Dpl : 2;
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UINT32 Present : 1;
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UINT32 LimitHigh : 4;
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UINT32 Software : 1;
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UINT32 Reserved : 1;
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UINT32 DefaultSize : 1;
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UINT32 Granularity : 1;
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UINT32 BaseHigh : 8;
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} Bits;
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UINT64 Uint64;
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} IA32_GDT;
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typedef struct {
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IA32_IDT_GATE_DESCRIPTOR Ia32IdtEntry;
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UINT32 Offset32To63;
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UINT32 Reserved;
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} X64_IDT_GATE_DESCRIPTOR;
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//
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// Page-Map Level-4 Offset (PML4) and
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// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
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//
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typedef union {
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struct {
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UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
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UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT64 Reserved:1; // Reserved
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UINT64 MustBeZero:2; // Must Be Zero
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UINT64 Available:3; // Available for use by system software
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UINT64 PageTableBaseAddress:40; // Page Table Base Address
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UINT64 AvabilableHigh:11; // Available for use by system software
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UINT64 Nx:1; // No Execute bit
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} Bits;
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UINT64 Uint64;
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} PAGE_MAP_AND_DIRECTORY_POINTER;
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//
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// Page Table Entry 4KB
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//
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typedef union {
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struct {
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UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
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UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page
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UINT64 PAT:1; //
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UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
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UINT64 Available:3; // Available for use by system software
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UINT64 PageTableBaseAddress:40; // Page Table Base Address
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UINT64 AvabilableHigh:11; // Available for use by system software
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UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution
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} Bits;
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UINT64 Uint64;
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} PAGE_TABLE_4K_ENTRY;
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//
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// Page Table Entry 2MB
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//
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typedef union {
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struct {
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UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
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UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page
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UINT64 MustBe1:1; // Must be 1
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UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
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UINT64 Available:3; // Available for use by system software
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UINT64 PAT:1; //
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UINT64 MustBeZero:8; // Must be zero;
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UINT64 PageTableBaseAddress:31; // Page Table Base Address
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UINT64 AvabilableHigh:11; // Available for use by system software
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UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution
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} Bits;
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UINT64 Uint64;
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} PAGE_TABLE_ENTRY;
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//
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// Page Table Entry 1GB
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//
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typedef union {
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struct {
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UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
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UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page
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UINT64 MustBe1:1; // Must be 1
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UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
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UINT64 Available:3; // Available for use by system software
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UINT64 PAT:1; //
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UINT64 MustBeZero:17; // Must be zero;
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UINT64 PageTableBaseAddress:22; // Page Table Base Address
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UINT64 AvabilableHigh:11; // Available for use by system software
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UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution
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} Bits;
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UINT64 Uint64;
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} PAGE_TABLE_1G_ENTRY;
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#pragma pack()
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#define CR0_WP BIT16
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#define IA32_PG_P BIT0
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#define IA32_PG_RW BIT1
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#define IA32_PG_PS BIT7
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#define PAGING_PAE_INDEX_MASK 0x1FF
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#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull
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#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull
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#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull
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#define PAGING_L1_ADDRESS_SHIFT 12
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#define PAGING_L2_ADDRESS_SHIFT 21
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#define PAGING_L3_ADDRESS_SHIFT 30
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#define PAGING_L4_ADDRESS_SHIFT 39
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#define PAGING_PML4E_NUMBER 4
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#define PAGE_TABLE_POOL_ALIGNMENT BASE_2MB
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#define PAGE_TABLE_POOL_UNIT_SIZE SIZE_2MB
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#define PAGE_TABLE_POOL_UNIT_PAGES EFI_SIZE_TO_PAGES (PAGE_TABLE_POOL_UNIT_SIZE)
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#define PAGE_TABLE_POOL_ALIGN_MASK \
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(~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1))
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typedef struct {
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VOID *NextPool;
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UINTN Offset;
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UINTN FreePages;
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} PAGE_TABLE_POOL;
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/**
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Check if Execute Disable Bit (IA32_EFER.NXE) should be enabled or not.
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@retval TRUE IA32_EFER.NXE should be enabled.
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@retval FALSE IA32_EFER.NXE should not be enabled.
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**/
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BOOLEAN
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IsEnableNonExecNeeded (
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VOID
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);
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/**
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Enable Execute Disable Bit.
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**/
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VOID
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EnableExecuteDisableBit (
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VOID
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);
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/**
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Split 2M page to 4K.
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@param[in] PhysicalAddress Start physical address the 2M page covered.
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@param[in, out] PageEntry2M Pointer to 2M page entry.
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@param[in] StackBase Stack base address.
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@param[in] StackSize Stack size.
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**/
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VOID
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Split2MPageTo4K (
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IN EFI_PHYSICAL_ADDRESS PhysicalAddress,
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IN OUT UINT64 *PageEntry2M,
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IN EFI_PHYSICAL_ADDRESS StackBase,
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IN UINTN StackSize
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);
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/**
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Allocates and fills in the Page Directory and Page Table Entries to
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establish a 1:1 Virtual to Physical mapping.
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@param[in] StackBase Stack base address.
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@param[in] StackSize Stack size.
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@return The address of 4 level page map.
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**/
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UINTN
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CreateIdentityMappingPageTables (
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IN EFI_PHYSICAL_ADDRESS StackBase,
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IN UINTN StackSize
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);
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/**
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Fix up the vector number in the vector code.
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@param VectorBase Base address of the vector handler.
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@param VectorNum Index of vector.
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**/
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VOID
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EFIAPI
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AsmVectorFixup (
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VOID *VectorBase,
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UINT8 VectorNum
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);
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/**
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Get the information of vector template.
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@param TemplateBase Base address of the template code.
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@return Size of the Template code.
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**/
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UINTN
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EFIAPI
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AsmGetVectorTemplatInfo (
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OUT VOID **TemplateBase
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);
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/**
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Clear legacy memory located at the first 4K-page.
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This function traverses the whole HOB list to check if memory from 0 to 4095
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exists and has not been allocated, and then clear it if so.
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@param HobStart The start of HobList passed to DxeCore.
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**/
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VOID
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ClearFirst4KPage (
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IN VOID *HobStart
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);
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/**
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Return configure status of NULL pointer detection feature.
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@return TRUE NULL pointer detection feature is enabled
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@return FALSE NULL pointer detection feature is disabled
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**/
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BOOLEAN
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IsNullDetectionEnabled (
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VOID
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);
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/**
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Prevent the memory pages used for page table from been overwritten.
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@param[in] PageTableBase Base address of page table (CR3).
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@param[in] Level4Paging Level 4 paging flag.
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**/
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VOID
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EnablePageTableProtection (
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IN UINTN PageTableBase,
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IN BOOLEAN Level4Paging
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);
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/**
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This API provides a way to allocate memory for page table.
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This API can be called more than once to allocate memory for page tables.
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Allocates the number of 4KB pages and returns a pointer to the allocated
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buffer. The buffer returned is aligned on a 4KB boundary.
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If Pages is 0, then NULL is returned.
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If there is not enough memory remaining to satisfy the request, then NULL is
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returned.
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@param Pages The number of 4 KB pages to allocate.
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@return A pointer to the allocated buffer or NULL if allocation fails.
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**/
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VOID *
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AllocatePageTableMemory (
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IN UINTN Pages
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);
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#endif
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