mirror of https://github.com/acidanthera/audk.git
789 lines
22 KiB
NASM
789 lines
22 KiB
NASM
;------------------------------------------------------------------------------ ;
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; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; Module Name:
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;
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; MpFuncs.nasm
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;
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; Abstract:
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;
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; This is the assembly code for MP support
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;
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;-------------------------------------------------------------------------------
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%include "MpEqu.inc"
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extern ASM_PFX(InitializeFloatingPointUnits)
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DEFAULT REL
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SECTION .text
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;-------------------------------------------------------------------------------------
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;RendezvousFunnelProc procedure follows. All APs execute their procedure. This
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;procedure serializes all the AP processors through an Init sequence. It must be
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;noted that APs arrive here very raw...ie: real mode, no stack.
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;ALSO THIS PROCEDURE IS EXECUTED BY APs ONLY ON 16 BIT MODE. HENCE THIS PROC
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;IS IN MACHINE CODE.
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;-------------------------------------------------------------------------------------
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global ASM_PFX(RendezvousFunnelProc)
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ASM_PFX(RendezvousFunnelProc):
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RendezvousFunnelProcStart:
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; At this point CS = 0x(vv00) and ip= 0x0.
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; Save BIST information to ebp firstly
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BITS 16
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mov ebp, eax ; Save BIST information
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mov ax, cs
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mov ds, ax
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mov es, ax
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mov ss, ax
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xor ax, ax
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mov fs, ax
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mov gs, ax
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mov si, BufferStartLocation
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mov ebx, [si]
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mov si, DataSegmentLocation
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mov edx, [si]
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;
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; Get start address of 32-bit code in low memory (<1MB)
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;
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mov edi, ModeTransitionMemoryLocation
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mov si, GdtrLocation
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o32 lgdt [cs:si]
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mov si, IdtrLocation
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o32 lidt [cs:si]
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;
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; Switch to protected mode
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;
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mov eax, cr0 ; Get control register 0
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or eax, 000000003h ; Set PE bit (bit #0) & MP
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mov cr0, eax
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; Switch to 32-bit code (>1MB)
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o32 jmp far [cs:di]
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;
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; Following code must be copied to memory with type of EfiBootServicesCode.
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; This is required if NX is enabled for EfiBootServicesCode of memory.
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;
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BITS 32
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Flat32Start: ; protected mode entry point
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mov ds, dx
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mov es, dx
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mov fs, dx
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mov gs, dx
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mov ss, dx
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;
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; Enable execute disable bit
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;
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mov esi, EnableExecuteDisableLocation
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cmp byte [ebx + esi], 0
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jz SkipEnableExecuteDisableBit
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mov ecx, 0c0000080h ; EFER MSR number
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rdmsr ; Read EFER
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bts eax, 11 ; Enable Execute Disable Bit
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wrmsr ; Write EFER
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SkipEnableExecuteDisableBit:
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;
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; Enable PAE
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;
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mov eax, cr4
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bts eax, 5
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mov esi, Enable5LevelPagingLocation
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cmp byte [ebx + esi], 0
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jz SkipEnable5LevelPaging
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;
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; Enable 5 Level Paging
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;
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bts eax, 12 ; Set LA57=1.
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SkipEnable5LevelPaging:
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mov cr4, eax
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;
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; Load page table
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;
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mov esi, Cr3Location ; Save CR3 in ecx
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mov ecx, [ebx + esi]
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mov cr3, ecx ; Load CR3
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;
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; Enable long mode
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;
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mov ecx, 0c0000080h ; EFER MSR number
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rdmsr ; Read EFER
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bts eax, 8 ; Set LME=1
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wrmsr ; Write EFER
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;
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; Enable paging
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;
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mov eax, cr0 ; Read CR0
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bts eax, 31 ; Set PG=1
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mov cr0, eax ; Write CR0
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;
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; Far jump to 64-bit code
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;
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mov edi, ModeHighMemoryLocation
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add edi, ebx
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jmp far [edi]
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BITS 64
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LongModeStart:
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mov esi, ebx
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lea edi, [esi + InitFlagLocation]
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cmp qword [edi], 1 ; ApInitConfig
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jnz GetApicId
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; Increment the number of APs executing here as early as possible
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; This is decremented in C code when AP is finished executing
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mov edi, esi
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add edi, NumApsExecutingLocation
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lock inc dword [edi]
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; AP init
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mov edi, esi
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add edi, LockLocation
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mov rax, NotVacantFlag
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TestLock:
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xchg qword [edi], rax
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cmp rax, NotVacantFlag
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jz TestLock
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lea ecx, [esi + ApIndexLocation]
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inc dword [ecx]
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mov ebx, [ecx]
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Releaselock:
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mov rax, VacantFlag
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xchg qword [edi], rax
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; program stack
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mov edi, esi
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add edi, StackSizeLocation
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mov eax, dword [edi]
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mov ecx, ebx
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inc ecx
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mul ecx ; EAX = StackSize * (CpuNumber + 1)
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mov edi, esi
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add edi, StackStartAddressLocation
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add rax, qword [edi]
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mov rsp, rax
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lea edi, [esi + SevEsIsEnabledLocation]
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cmp byte [edi], 1 ; SevEsIsEnabled
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jne CProcedureInvoke
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;
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; program GHCB
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; Each page after the GHCB is a per-CPU page, so the calculation programs
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; a GHCB to be every 8KB.
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;
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mov eax, SIZE_4KB
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shl eax, 1 ; EAX = SIZE_4K * 2
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mov ecx, ebx
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mul ecx ; EAX = SIZE_4K * 2 * CpuNumber
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mov edi, esi
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add edi, GhcbBaseLocation
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add rax, qword [edi]
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mov rdx, rax
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shr rdx, 32
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mov rcx, 0xc0010130
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wrmsr
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jmp CProcedureInvoke
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GetApicId:
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lea edi, [esi + SevEsIsEnabledLocation]
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cmp byte [edi], 1 ; SevEsIsEnabled
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jne DoCpuid
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;
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; Since we don't have a stack yet, we can't take a #VC
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; exception. Use the GHCB protocol to perform the CPUID
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; calls.
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;
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mov rcx, 0xc0010130
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rdmsr
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shl rdx, 32
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or rax, rdx
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mov rdi, rax ; RDI now holds the original GHCB GPA
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mov rdx, 0 ; CPUID function 0
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mov rax, 0 ; RAX register requested
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or rax, 4
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wrmsr
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rep vmmcall
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rdmsr
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cmp edx, 0bh
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jb NoX2ApicSevEs ; CPUID level below CPUID_EXTENDED_TOPOLOGY
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mov rdx, 0bh ; CPUID function 0x0b
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mov rax, 040000000h ; RBX register requested
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or rax, 4
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wrmsr
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rep vmmcall
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rdmsr
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test edx, 0ffffh
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jz NoX2ApicSevEs ; CPUID.0BH:EBX[15:0] is zero
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mov rdx, 0bh ; CPUID function 0x0b
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mov rax, 0c0000000h ; RDX register requested
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or rax, 4
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wrmsr
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rep vmmcall
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rdmsr
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; Processor is x2APIC capable; 32-bit x2APIC ID is now in EDX
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jmp RestoreGhcb
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NoX2ApicSevEs:
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; Processor is not x2APIC capable, so get 8-bit APIC ID
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mov rdx, 1 ; CPUID function 1
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mov rax, 040000000h ; RBX register requested
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or rax, 4
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wrmsr
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rep vmmcall
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rdmsr
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shr edx, 24
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RestoreGhcb:
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mov rbx, rdx ; Save x2APIC/APIC ID
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mov rdx, rdi ; RDI holds the saved GHCB GPA
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shr rdx, 32
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mov eax, edi
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wrmsr
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mov rdx, rbx
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; x2APIC ID or APIC ID is in EDX
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jmp GetProcessorNumber
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DoCpuid:
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mov eax, 0
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cpuid
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cmp eax, 0bh
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jb NoX2Apic ; CPUID level below CPUID_EXTENDED_TOPOLOGY
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mov eax, 0bh
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xor ecx, ecx
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cpuid
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test ebx, 0ffffh
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jz NoX2Apic ; CPUID.0BH:EBX[15:0] is zero
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; Processor is x2APIC capable; 32-bit x2APIC ID is already in EDX
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jmp GetProcessorNumber
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NoX2Apic:
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; Processor is not x2APIC capable, so get 8-bit APIC ID
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mov eax, 1
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cpuid
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shr ebx, 24
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mov edx, ebx
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GetProcessorNumber:
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;
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; Get processor number for this AP
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; Note that BSP may become an AP due to SwitchBsp()
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;
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xor ebx, ebx
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lea eax, [esi + CpuInfoLocation]
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mov edi, [eax]
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GetNextProcNumber:
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cmp dword [edi], edx ; APIC ID match?
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jz ProgramStack
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add edi, 20
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inc ebx
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jmp GetNextProcNumber
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ProgramStack:
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mov rsp, qword [edi + 12]
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CProcedureInvoke:
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push rbp ; Push BIST data at top of AP stack
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xor rbp, rbp ; Clear ebp for call stack trace
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push rbp
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mov rbp, rsp
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mov rax, qword [esi + InitializeFloatingPointUnitsAddress]
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sub rsp, 20h
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call rax ; Call assembly function to initialize FPU per UEFI spec
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add rsp, 20h
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mov edx, ebx ; edx is ApIndex
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mov ecx, esi
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add ecx, LockLocation ; rcx is address of exchange info data buffer
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mov edi, esi
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add edi, ApProcedureLocation
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mov rax, qword [edi]
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sub rsp, 20h
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call rax ; Invoke C function
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add rsp, 20h
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jmp $ ; Should never reach here
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RendezvousFunnelProcEnd:
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;-------------------------------------------------------------------------------------
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;SwitchToRealProc procedure follows.
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;ALSO THIS PROCEDURE IS EXECUTED BY APs TRANSITIONING TO 16 BIT MODE. HENCE THIS PROC
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;IS IN MACHINE CODE.
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; SwitchToRealProc (UINTN BufferStart, UINT16 Code16, UINT16 Code32, UINTN StackStart)
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; rcx - Buffer Start
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; rdx - Code16 Selector Offset
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; r8 - Code32 Selector Offset
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; r9 - Stack Start
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;-------------------------------------------------------------------------------------
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global ASM_PFX(SwitchToRealProc)
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ASM_PFX(SwitchToRealProc):
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SwitchToRealProcStart:
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BITS 64
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cli
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;
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; Get RDX reset value before changing stacks since the
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; new stack won't be able to accomodate a #VC exception.
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;
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push rax
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push rbx
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push rcx
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push rdx
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mov rax, 1
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cpuid
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mov rsi, rax ; Save off the reset value for RDX
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pop rdx
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pop rcx
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pop rbx
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pop rax
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;
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; Establish stack below 1MB
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;
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mov rsp, r9
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;
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; Push ultimate Reset Vector onto the stack
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;
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mov rax, rcx
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shr rax, 4
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push word 0x0002 ; RFLAGS
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push ax ; CS
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push word 0x0000 ; RIP
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push word 0x0000 ; For alignment, will be discarded
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;
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; Get address of "16-bit operand size" label
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;
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lea rbx, [PM16Mode]
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;
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; Push addresses used to change to compatibility mode
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;
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lea rax, [CompatMode]
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push r8
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push rax
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;
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; Clear R8 - R15, for reset, before going into 32-bit mode
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;
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xor r8, r8
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xor r9, r9
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xor r10, r10
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xor r11, r11
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xor r12, r12
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xor r13, r13
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xor r14, r14
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xor r15, r15
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;
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; Far return into 32-bit mode
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;
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o64 retf
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BITS 32
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CompatMode:
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;
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; Set up stack to prepare for exiting protected mode
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;
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push edx ; Code16 CS
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push ebx ; PM16Mode label address
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;
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; Disable paging
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;
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mov eax, cr0 ; Read CR0
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btr eax, 31 ; Set PG=0
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mov cr0, eax ; Write CR0
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;
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; Disable long mode
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;
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mov ecx, 0c0000080h ; EFER MSR number
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rdmsr ; Read EFER
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btr eax, 8 ; Set LME=0
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wrmsr ; Write EFER
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;
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; Disable PAE
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;
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mov eax, cr4 ; Read CR4
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btr eax, 5 ; Set PAE=0
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mov cr4, eax ; Write CR4
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mov edx, esi ; Restore RDX reset value
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;
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; Switch to 16-bit operand size
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;
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retf
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BITS 16
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;
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; At entry to this label
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; - RDX will have its reset value
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; - On the top of the stack
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; - Alignment data (two bytes) to be discarded
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; - IP for Real Mode (two bytes)
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; - CS for Real Mode (two bytes)
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;
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; This label is also used with AsmRelocateApLoop. During MP finalization,
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; the code from PM16Mode to SwitchToRealProcEnd is copied to the start of
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; the WakeupBuffer, allowing a parked AP to be booted by an OS.
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;
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PM16Mode:
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mov eax, cr0 ; Read CR0
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btr eax, 0 ; Set PE=0
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mov cr0, eax ; Write CR0
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pop ax ; Discard alignment data
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;
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; Clear registers (except RDX and RSP) before going into 16-bit mode
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;
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xor eax, eax
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xor ebx, ebx
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xor ecx, ecx
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xor esi, esi
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xor edi, edi
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xor ebp, ebp
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iret
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SwitchToRealProcEnd:
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;-------------------------------------------------------------------------------------
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; AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfApStack, CountTofinish, Pm16CodeSegment, SevEsAPJumpTable, WakeupBuffer);
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;-------------------------------------------------------------------------------------
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global ASM_PFX(AsmRelocateApLoop)
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ASM_PFX(AsmRelocateApLoop):
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AsmRelocateApLoopStart:
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BITS 64
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cmp qword [rsp + 56], 0 ; SevEsAPJumpTable
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je NoSevEs
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;
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; Perform some SEV-ES related setup before leaving 64-bit mode
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;
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push rcx
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push rdx
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;
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; Get the RDX reset value using CPUID
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;
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mov rax, 1
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cpuid
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mov rsi, rax ; Save off the reset value for RDX
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;
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; Prepare the GHCB for the AP_HLT_LOOP VMGEXIT call
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; - Must be done while in 64-bit long mode so that writes to
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; the GHCB memory will be unencrypted.
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; - No NAE events can be generated once this is set otherwise
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; the AP_RESET_HOLD SW_EXITCODE will be overwritten.
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;
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mov rcx, 0xc0010130
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rdmsr ; Retrieve current GHCB address
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shl rdx, 32
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or rdx, rax
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mov rdi, rdx
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xor rax, rax
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mov rcx, 0x800
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shr rcx, 3
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rep stosq ; Clear the GHCB
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mov rax, 0x80000004 ; VMGEXIT AP_RESET_HOLD
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mov [rdx + 0x390], rax
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mov rax, 114 ; Set SwExitCode valid bit
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bts [rdx + 0x3f0], rax
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inc rax ; Set SwExitInfo1 valid bit
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bts [rdx + 0x3f0], rax
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inc rax ; Set SwExitInfo2 valid bit
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bts [rdx + 0x3f0], rax
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pop rdx
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pop rcx
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NoSevEs:
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cli ; Disable interrupt before switching to 32-bit mode
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mov rax, [rsp + 40] ; CountTofinish
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lock dec dword [rax] ; (*CountTofinish)--
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mov r10, [rsp + 48] ; Pm16CodeSegment
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mov rax, [rsp + 56] ; SevEsAPJumpTable
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mov rbx, [rsp + 64] ; WakeupBuffer
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mov rsp, r9 ; TopOfApStack
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push rax ; Save SevEsAPJumpTable
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push rbx ; Save WakeupBuffer
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push r10 ; Save Pm16CodeSegment
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push rcx ; Save MwaitSupport
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push rdx ; Save ApTargetCState
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lea rax, [PmEntry] ; rax <- The start address of transition code
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push r8
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push rax
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;
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; Clear R8 - R15, for reset, before going into 32-bit mode
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;
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xor r8, r8
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xor r9, r9
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xor r10, r10
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xor r11, r11
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xor r12, r12
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xor r13, r13
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xor r14, r14
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xor r15, r15
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;
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; Far return into 32-bit mode
|
|
;
|
|
o64 retf
|
|
|
|
BITS 32
|
|
PmEntry:
|
|
mov eax, cr0
|
|
btr eax, 31 ; Clear CR0.PG
|
|
mov cr0, eax ; Disable paging and caches
|
|
|
|
mov ecx, 0xc0000080
|
|
rdmsr
|
|
and ah, ~ 1 ; Clear LME
|
|
wrmsr
|
|
mov eax, cr4
|
|
and al, ~ (1 << 5) ; Clear PAE
|
|
mov cr4, eax
|
|
|
|
pop edx
|
|
add esp, 4
|
|
pop ecx,
|
|
add esp, 4
|
|
|
|
MwaitCheck:
|
|
cmp cl, 1 ; Check mwait-monitor support
|
|
jnz HltLoop
|
|
mov ebx, edx ; Save C-State to ebx
|
|
MwaitLoop:
|
|
cli
|
|
mov eax, esp ; Set Monitor Address
|
|
xor ecx, ecx ; ecx = 0
|
|
xor edx, edx ; edx = 0
|
|
monitor
|
|
mov eax, ebx ; Mwait Cx, Target C-State per eax[7:4]
|
|
shl eax, 4
|
|
mwait
|
|
jmp MwaitLoop
|
|
|
|
HltLoop:
|
|
pop edx ; PM16CodeSegment
|
|
add esp, 4
|
|
pop ebx ; WakeupBuffer
|
|
add esp, 4
|
|
pop eax ; SevEsAPJumpTable
|
|
add esp, 4
|
|
cmp eax, 0 ; Check for SEV-ES
|
|
je DoHlt
|
|
|
|
cli
|
|
;
|
|
; SEV-ES is enabled, use VMGEXIT (GHCB information already
|
|
; set by caller)
|
|
;
|
|
BITS 64
|
|
rep vmmcall
|
|
BITS 32
|
|
|
|
;
|
|
; Back from VMGEXIT AP_HLT_LOOP
|
|
; Push the FLAGS/CS/IP values to use
|
|
;
|
|
push word 0x0002 ; EFLAGS
|
|
xor ecx, ecx
|
|
mov cx, [eax + 2] ; CS
|
|
push cx
|
|
mov cx, [eax] ; IP
|
|
push cx
|
|
push word 0x0000 ; For alignment, will be discarded
|
|
|
|
push edx
|
|
push ebx
|
|
|
|
mov edx, esi ; Restore RDX reset value
|
|
|
|
retf
|
|
|
|
DoHlt:
|
|
cli
|
|
hlt
|
|
jmp DoHlt
|
|
|
|
BITS 64
|
|
AsmRelocateApLoopEnd:
|
|
|
|
;-------------------------------------------------------------------------------------
|
|
; AsmGetAddressMap (&AddressMap);
|
|
;-------------------------------------------------------------------------------------
|
|
global ASM_PFX(AsmGetAddressMap)
|
|
ASM_PFX(AsmGetAddressMap):
|
|
lea rax, [ASM_PFX(RendezvousFunnelProc)]
|
|
mov qword [rcx], rax
|
|
mov qword [rcx + 8h], LongModeStart - RendezvousFunnelProcStart
|
|
mov qword [rcx + 10h], RendezvousFunnelProcEnd - RendezvousFunnelProcStart
|
|
lea rax, [ASM_PFX(AsmRelocateApLoop)]
|
|
mov qword [rcx + 18h], rax
|
|
mov qword [rcx + 20h], AsmRelocateApLoopEnd - AsmRelocateApLoopStart
|
|
mov qword [rcx + 28h], Flat32Start - RendezvousFunnelProcStart
|
|
mov qword [rcx + 30h], SwitchToRealProcEnd - SwitchToRealProcStart ; SwitchToRealSize
|
|
mov qword [rcx + 38h], SwitchToRealProcStart - RendezvousFunnelProcStart ; SwitchToRealOffset
|
|
mov qword [rcx + 40h], SwitchToRealProcStart - Flat32Start ; SwitchToRealNoNxOffset
|
|
mov qword [rcx + 48h], PM16Mode - RendezvousFunnelProcStart ; SwitchToRealPM16ModeOffset
|
|
mov qword [rcx + 50h], SwitchToRealProcEnd - PM16Mode ; SwitchToRealPM16ModeSize
|
|
ret
|
|
|
|
;-------------------------------------------------------------------------------------
|
|
;AsmExchangeRole procedure follows. This procedure executed by current BSP, that is
|
|
;about to become an AP. It switches its stack with the current AP.
|
|
;AsmExchangeRole (IN CPU_EXCHANGE_INFO *MyInfo, IN CPU_EXCHANGE_INFO *OthersInfo);
|
|
;-------------------------------------------------------------------------------------
|
|
global ASM_PFX(AsmExchangeRole)
|
|
ASM_PFX(AsmExchangeRole):
|
|
; DO NOT call other functions in this function, since 2 CPU may use 1 stack
|
|
; at the same time. If 1 CPU try to call a function, stack will be corrupted.
|
|
|
|
push rax
|
|
push rbx
|
|
push rcx
|
|
push rdx
|
|
push rsi
|
|
push rdi
|
|
push rbp
|
|
push r8
|
|
push r9
|
|
push r10
|
|
push r11
|
|
push r12
|
|
push r13
|
|
push r14
|
|
push r15
|
|
|
|
mov rax, cr0
|
|
push rax
|
|
|
|
mov rax, cr4
|
|
push rax
|
|
|
|
; rsi contains MyInfo pointer
|
|
mov rsi, rcx
|
|
|
|
; rdi contains OthersInfo pointer
|
|
mov rdi, rdx
|
|
|
|
;Store EFLAGS, GDTR and IDTR regiter to stack
|
|
pushfq
|
|
sgdt [rsi + 16]
|
|
sidt [rsi + 26]
|
|
|
|
; Store the its StackPointer
|
|
mov [rsi + 8], rsp
|
|
|
|
; update its switch state to STORED
|
|
mov byte [rsi], CPU_SWITCH_STATE_STORED
|
|
|
|
WaitForOtherStored:
|
|
; wait until the other CPU finish storing its state
|
|
cmp byte [rdi], CPU_SWITCH_STATE_STORED
|
|
jz OtherStored
|
|
pause
|
|
jmp WaitForOtherStored
|
|
|
|
OtherStored:
|
|
; Since another CPU already stored its state, load them
|
|
; load GDTR value
|
|
lgdt [rdi + 16]
|
|
|
|
; load IDTR value
|
|
lidt [rdi + 26]
|
|
|
|
; load its future StackPointer
|
|
mov rsp, [rdi + 8]
|
|
|
|
; update the other CPU's switch state to LOADED
|
|
mov byte [rdi], CPU_SWITCH_STATE_LOADED
|
|
|
|
WaitForOtherLoaded:
|
|
; wait until the other CPU finish loading new state,
|
|
; otherwise the data in stack may corrupt
|
|
cmp byte [rsi], CPU_SWITCH_STATE_LOADED
|
|
jz OtherLoaded
|
|
pause
|
|
jmp WaitForOtherLoaded
|
|
|
|
OtherLoaded:
|
|
; since the other CPU already get the data it want, leave this procedure
|
|
popfq
|
|
|
|
pop rax
|
|
mov cr4, rax
|
|
|
|
pop rax
|
|
mov cr0, rax
|
|
|
|
pop r15
|
|
pop r14
|
|
pop r13
|
|
pop r12
|
|
pop r11
|
|
pop r10
|
|
pop r9
|
|
pop r8
|
|
pop rbp
|
|
pop rdi
|
|
pop rsi
|
|
pop rdx
|
|
pop rcx
|
|
pop rbx
|
|
pop rax
|
|
|
|
ret
|