mirror of https://github.com/acidanthera/audk.git
519 lines
15 KiB
NASM
519 lines
15 KiB
NASM
;------------------------------------------------------------------------------ ;
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; Copyright (c) 2021, AMD Inc. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; Module Name:
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;
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; AmdSev.nasm
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;
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; Abstract:
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;
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; This provides helper used by the MpFunc.nasm. If AMD SEV-ES is active
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; then helpers perform the additional setups (such as GHCB).
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;
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;-------------------------------------------------------------------------------
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%define SIZE_4KB 0x1000
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RegisterGhcbGpa:
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;
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; Register GHCB GPA when SEV-SNP is enabled
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;
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lea edi, [esi + MP_CPU_EXCHANGE_INFO_FIELD (SevSnpIsEnabled)]
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cmp byte [edi], 1 ; SevSnpIsEnabled
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jne RegisterGhcbGpaDone
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; Save the rdi and rsi to used for later comparison
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push rdi
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push rsi
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mov edi, eax
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mov esi, edx
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or eax, 18 ; Ghcb registration request
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wrmsr
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rep vmmcall
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rdmsr
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mov r12, rax
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and r12, 0fffh
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cmp r12, 19 ; Ghcb registration response
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jne GhcbGpaRegisterFailure
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; Verify that GPA is not changed
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and eax, 0fffff000h
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cmp edi, eax
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jne GhcbGpaRegisterFailure
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cmp esi, edx
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jne GhcbGpaRegisterFailure
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pop rsi
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pop rdi
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jmp RegisterGhcbGpaDone
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;
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; Request the guest termination
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;
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GhcbGpaRegisterFailure:
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xor edx, edx
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mov eax, 256 ; GHCB terminate
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wrmsr
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rep vmmcall
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; We should not return from the above terminate request, but if we do
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; then enter into the hlt loop.
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DoHltLoop:
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cli
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hlt
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jmp DoHltLoop
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RegisterGhcbGpaDone:
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OneTimeCallRet RegisterGhcbGpa
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;
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; The function checks whether SEV-ES is enabled, if enabled
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; then setup the GHCB page.
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;
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SevEsSetupGhcb:
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lea edi, [esi + MP_CPU_EXCHANGE_INFO_FIELD (SevEsIsEnabled)]
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cmp byte [edi], 1 ; SevEsIsEnabled
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jne SevEsSetupGhcbExit
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;
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; program GHCB
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; Each page after the GHCB is a per-CPU page, so the calculation programs
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; a GHCB to be every 8KB.
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;
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mov eax, SIZE_4KB
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shl eax, 1 ; EAX = SIZE_4K * 2
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mov ecx, ebx
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mul ecx ; EAX = SIZE_4K * 2 * CpuNumber
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mov edi, esi
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add edi, MP_CPU_EXCHANGE_INFO_FIELD (GhcbBase)
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add rax, qword [edi]
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mov rdx, rax
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shr rdx, 32
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mov rcx, 0xc0010130
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OneTimeCall RegisterGhcbGpa
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wrmsr
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SevEsSetupGhcbExit:
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OneTimeCallRet SevEsSetupGhcb
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;
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; The function checks whether SEV-ES is enabled, if enabled, use
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; the GHCB
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;
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SevEsGetApicId:
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lea edi, [esi + MP_CPU_EXCHANGE_INFO_FIELD (SevEsIsEnabled)]
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cmp byte [edi], 1 ; SevEsIsEnabled
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jne SevEsGetApicIdExit
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;
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; Since we don't have a stack yet, we can't take a #VC
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; exception. Use the GHCB protocol to perform the CPUID
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; calls.
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;
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mov rcx, 0xc0010130
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rdmsr
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shl rdx, 32
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or rax, rdx
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mov rdi, rax ; RDI now holds the original GHCB GPA
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;
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; For SEV-SNP, the recommended handling for getting the x2APIC ID
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; would be to use the SNP CPUID table to fetch CPUID.00H:EAX and
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; CPUID:0BH:EBX[15:0] instead of the GHCB MSR protocol vmgexits
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; below.
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;
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; To avoid the unecessary ugliness to accomplish that here, the BSP
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; has performed these checks in advance (where #VC handler handles
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; the CPUID table lookups automatically) and cached them in a flag
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; so those checks can be skipped here.
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;
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mov eax, [esi + MP_CPU_EXCHANGE_INFO_FIELD (SevSnpIsEnabled)]
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cmp al, 1
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jne CheckExtTopoAvail
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;
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; Even with SEV-SNP, the actual x2APIC ID in CPUID.0BH:EDX
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; fetched from the hypervisor the same way SEV-ES does it.
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;
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mov eax, [esi + MP_CPU_EXCHANGE_INFO_FIELD (ExtTopoAvail)]
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cmp al, 1
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je GetApicIdSevEs
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; The 8-bit APIC ID fallback is also the same as with SEV-ES
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jmp NoX2ApicSevEs
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CheckExtTopoAvail:
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mov rdx, 0 ; CPUID function 0
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mov rax, 0 ; RAX register requested
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or rax, 4
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wrmsr
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rep vmmcall
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rdmsr
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cmp edx, 0bh
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jb NoX2ApicSevEs ; CPUID level below CPUID_EXTENDED_TOPOLOGY
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mov rdx, 0bh ; CPUID function 0x0b
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mov rax, 040000000h ; RBX register requested
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or rax, 4
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wrmsr
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rep vmmcall
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rdmsr
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test edx, 0ffffh
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jz NoX2ApicSevEs ; CPUID.0BH:EBX[15:0] is zero
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GetApicIdSevEs:
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mov rdx, 0bh ; CPUID function 0x0b
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mov rax, 0c0000000h ; RDX register requested
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or rax, 4
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wrmsr
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rep vmmcall
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rdmsr
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; Processor is x2APIC capable; 32-bit x2APIC ID is now in EDX
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jmp RestoreGhcb
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NoX2ApicSevEs:
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; Processor is not x2APIC capable, so get 8-bit APIC ID
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mov rdx, 1 ; CPUID function 1
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mov rax, 040000000h ; RBX register requested
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or rax, 4
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wrmsr
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rep vmmcall
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rdmsr
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shr edx, 24
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RestoreGhcb:
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mov rbx, rdx ; Save x2APIC/APIC ID
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mov rdx, rdi ; RDI holds the saved GHCB GPA
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shr rdx, 32
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mov eax, edi
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wrmsr
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mov rdx, rbx
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; x2APIC ID or APIC ID is in EDX
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jmp GetProcessorNumber
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SevEsGetApicIdExit:
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OneTimeCallRet SevEsGetApicId
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;-------------------------------------------------------------------------------------
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;SwitchToRealProc procedure follows.
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;ALSO THIS PROCEDURE IS EXECUTED BY APs TRANSITIONING TO 16 BIT MODE. HENCE THIS PROC
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;IS IN MACHINE CODE.
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; SwitchToRealProc (UINTN BufferStart, UINT16 Code16, UINT16 Code32, UINTN StackStart)
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; rcx - Buffer Start
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; rdx - Code16 Selector Offset
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; r8 - Code32 Selector Offset
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; r9 - Stack Start
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;-------------------------------------------------------------------------------------
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SwitchToRealProcStart:
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BITS 64
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cli
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;
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; Get RDX reset value before changing stacks since the
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; new stack won't be able to accomodate a #VC exception.
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;
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push rax
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push rbx
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push rcx
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push rdx
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mov rax, 1
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cpuid
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mov rsi, rax ; Save off the reset value for RDX
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pop rdx
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pop rcx
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pop rbx
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pop rax
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;
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; Establish stack below 1MB
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;
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mov rsp, r9
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;
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; Push ultimate Reset Vector onto the stack
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;
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mov rax, rcx
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shr rax, 4
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push word 0x0002 ; RFLAGS
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push ax ; CS
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push word 0x0000 ; RIP
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push word 0x0000 ; For alignment, will be discarded
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;
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; Get address of "16-bit operand size" label
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;
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lea rbx, [PM16Mode]
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;
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; Push addresses used to change to compatibility mode
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;
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lea rax, [CompatMode]
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push r8
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push rax
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;
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; Clear R8 - R15, for reset, before going into 32-bit mode
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;
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xor r8, r8
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xor r9, r9
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xor r10, r10
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xor r11, r11
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xor r12, r12
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xor r13, r13
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xor r14, r14
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xor r15, r15
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;
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; Far return into 32-bit mode
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;
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retfq
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BITS 32
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CompatMode:
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;
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; Set up stack to prepare for exiting protected mode
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;
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push edx ; Code16 CS
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push ebx ; PM16Mode label address
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;
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; Disable paging
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;
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mov eax, cr0 ; Read CR0
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btr eax, 31 ; Set PG=0
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mov cr0, eax ; Write CR0
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;
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; Disable long mode
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;
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mov ecx, 0c0000080h ; EFER MSR number
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rdmsr ; Read EFER
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btr eax, 8 ; Set LME=0
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wrmsr ; Write EFER
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;
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; Disable PAE
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;
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mov eax, cr4 ; Read CR4
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btr eax, 5 ; Set PAE=0
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mov cr4, eax ; Write CR4
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mov edx, esi ; Restore RDX reset value
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;
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; Switch to 16-bit operand size
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;
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retf
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BITS 16
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;
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; At entry to this label
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; - RDX will have its reset value
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; - On the top of the stack
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; - Alignment data (two bytes) to be discarded
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; - IP for Real Mode (two bytes)
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; - CS for Real Mode (two bytes)
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;
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; This label is also used with AsmRelocateApLoop. During MP finalization,
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; the code from PM16Mode to SwitchToRealProcEnd is copied to the start of
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; the WakeupBuffer, allowing a parked AP to be booted by an OS.
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;
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PM16Mode:
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mov eax, cr0 ; Read CR0
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btr eax, 0 ; Set PE=0
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mov cr0, eax ; Write CR0
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pop ax ; Discard alignment data
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;
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; Clear registers (except RDX and RSP) before going into 16-bit mode
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;
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xor eax, eax
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xor ebx, ebx
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xor ecx, ecx
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xor esi, esi
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xor edi, edi
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xor ebp, ebp
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iret
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SwitchToRealProcEnd:
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;-------------------------------------------------------------------------------------
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; AsmRelocateApLoopAmdSev (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfApStack, CountTofinish, Pm16CodeSegment, SevEsAPJumpTable, WakeupBuffer);
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;-------------------------------------------------------------------------------------
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AsmRelocateApLoopAmdSevStart:
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BITS 64
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cmp qword [rsp + 56], 0 ; SevEsAPJumpTable
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je NoSevEsAmdSev
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;
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; Perform some SEV-ES related setup before leaving 64-bit mode
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;
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push rcx
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push rdx
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;
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; Get the RDX reset value using CPUID
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;
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mov rax, 1
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cpuid
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mov rsi, rax ; Save off the reset value for RDX
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;
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; Prepare the GHCB for the AP_HLT_LOOP VMGEXIT call
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; - Must be done while in 64-bit long mode so that writes to
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; the GHCB memory will be unencrypted.
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; - No NAE events can be generated once this is set otherwise
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; the AP_RESET_HOLD SW_EXITCODE will be overwritten.
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;
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mov rcx, 0xc0010130
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rdmsr ; Retrieve current GHCB address
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shl rdx, 32
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or rdx, rax
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mov rdi, rdx
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xor rax, rax
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mov rcx, 0x800
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shr rcx, 3
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rep stosq ; Clear the GHCB
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mov rax, 0x80000004 ; VMGEXIT AP_RESET_HOLD
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mov [rdx + 0x390], rax
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mov rax, 114 ; Set SwExitCode valid bit
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bts [rdx + 0x3f0], rax
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inc rax ; Set SwExitInfo1 valid bit
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bts [rdx + 0x3f0], rax
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inc rax ; Set SwExitInfo2 valid bit
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bts [rdx + 0x3f0], rax
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pop rdx
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pop rcx
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NoSevEsAmdSev:
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cli ; Disable interrupt before switching to 32-bit mode
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mov rax, [rsp + 40] ; CountTofinish
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lock dec dword [rax] ; (*CountTofinish)--
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mov r10, [rsp + 48] ; Pm16CodeSegment
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mov rax, [rsp + 56] ; SevEsAPJumpTable
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mov rbx, [rsp + 64] ; WakeupBuffer
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mov rsp, r9 ; TopOfApStack
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push rax ; Save SevEsAPJumpTable
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push rbx ; Save WakeupBuffer
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push r10 ; Save Pm16CodeSegment
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push rcx ; Save MwaitSupport
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push rdx ; Save ApTargetCState
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lea rax, [PmEntryAmdSev] ; rax <- The start address of transition code
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push r8
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push rax
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;
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; Clear R8 - R15, for reset, before going into 32-bit mode
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;
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xor r8, r8
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xor r9, r9
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xor r10, r10
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xor r11, r11
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xor r12, r12
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xor r13, r13
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xor r14, r14
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xor r15, r15
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;
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; Far return into 32-bit mode
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;
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o64 retf
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BITS 32
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PmEntryAmdSev:
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mov eax, cr0
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btr eax, 31 ; Clear CR0.PG
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mov cr0, eax ; Disable paging and caches
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mov ecx, 0xc0000080
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rdmsr
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and ah, ~ 1 ; Clear LME
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wrmsr
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mov eax, cr4
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and al, ~ (1 << 5) ; Clear PAE
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mov cr4, eax
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pop edx
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add esp, 4
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pop ecx,
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add esp, 4
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MwaitCheckAmdSev:
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cmp cl, 1 ; Check mwait-monitor support
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jnz HltLoopAmdSev
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mov ebx, edx ; Save C-State to ebx
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MwaitLoopAmdSev:
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cli
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mov eax, esp ; Set Monitor Address
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xor ecx, ecx ; ecx = 0
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xor edx, edx ; edx = 0
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monitor
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mov eax, ebx ; Mwait Cx, Target C-State per eax[7:4]
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shl eax, 4
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mwait
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jmp MwaitLoopAmdSev
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HltLoopAmdSev:
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pop edx ; PM16CodeSegment
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add esp, 4
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pop ebx ; WakeupBuffer
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add esp, 4
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pop eax ; SevEsAPJumpTable
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add esp, 4
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cmp eax, 0 ; Check for SEV-ES
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je DoHltAmdSev
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cli
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;
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; SEV-ES is enabled, use VMGEXIT (GHCB information already
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; set by caller)
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;
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BITS 64
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rep vmmcall
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BITS 32
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;
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; Back from VMGEXIT AP_HLT_LOOP
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; Push the FLAGS/CS/IP values to use
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;
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push word 0x0002 ; EFLAGS
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xor ecx, ecx
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mov cx, [eax + 2] ; CS
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push cx
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mov cx, [eax] ; IP
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push cx
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push word 0x0000 ; For alignment, will be discarded
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push edx
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push ebx
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mov edx, esi ; Restore RDX reset value
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retf
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DoHltAmdSev:
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cli
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hlt
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jmp DoHltAmdSev
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BITS 64
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AsmRelocateApLoopAmdSevEnd:
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