mirror of https://github.com/acidanthera/audk.git
1147 lines
31 KiB
C
1147 lines
31 KiB
C
/** @file
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Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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**/
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#include "CommonHeader.h"
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#include "Platform.h"
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#include <Library/PciCf8Lib.h>
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#include "PlatformBaseAddresses.h"
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#include "PchAccess.h"
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#include <Guid/PlatformInfo.h>
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#include "Platform.h"
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#include "PchCommonDefinitions.h"
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#include <Ppi/MfgMemoryTest.h>
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#include <Guid/SetupVariable.h>
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#include <Guid/Vlv2Variable.h>
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#include <Ppi/fTPMPolicy.h>
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//
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// Start::Alpine Valley platform
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//
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enum {
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SMBUS_READ_BYTE,
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SMBUS_WRITE_BYTE,
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SMBUS_READ_BLOCK,
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SMBUS_WRITE_BLOCK
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};
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#define EC_BASE 0xE0000000
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//
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// DEVICE 0 (Memroy Controller Hub)
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//
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#define MC_BUS 0x00
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#define MC_DEV 0x00
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#define MC_FUN 0x00
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#define MC_DEV_FUN (MC_DEV << 3)
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#define MC_BUS_DEV_FUN ((MC_BUS << 8) + MC_DEV_FUN)
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//
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// SysCtl SMBus address and block size
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//
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#define AV_SC_SMBUS_ADDRESS 0x60
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#define AV_SC_BYTE_LEN 1
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#define AV_SC_BLOCK_LEN 4
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#define AV_SC_SMBUS_WRCMD 1
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#define AV_SC_SMBUS_RDCMD 0
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//
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// SysCtl registers offset
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//
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#define AV_SC_REG_PLATFORM_ID 24 // 0x18
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#define AV_SC_REG_BOARD_ID 28 // 0x1C
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#define AV_SC_REG_FAB_ID 32 // 0x20
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#define AV_SC_REG_ECO_ID 68 // 0x44
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#define AV_SC_REG_DDR_DAUGHTER_CARD_ID 144 // 0x90
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#define AV_SC_REG_SODIMM_CONFIG 36
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//
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// ID values
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//
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#define AV_SC_PLATFORM_ID_TABLET 0
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#define AV_SC_PLATFORM_ID_NETBOOK 2
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#define AV_SC_PLATFORM_ID_INTERPOSER 3 // Configuration TBD
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#define AV_SC_BOARD_ID_AV_SVP 1492
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#define BUS_TRIES 3 // How many times to retry on Bus Errors
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#define GTT_SIZE_1MB 1
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#define GTT_SIZE_2MB 2
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#define PciCfg16Read( PciExpressBase, Bus, Device, Function, Register ) \
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MmioRead16(PciExpressBase + \
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(UINTN)(Bus << 20) + \
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(UINTN)(Device << 15) + \
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(UINTN)(Function << 12) + \
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(UINTN)(Register))
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#define PciCfg16Write( PciExpressBase, Bus, Device, Function, Register, Data ) \
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MmioWrite16(PciExpressBase + \
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(UINTN)(Bus << 20) + \
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(UINTN)(Device << 15) + \
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(UINTN)(Function << 12) + \
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(UINTN)(Register), \
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(UINT16)Data)
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//
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//Memory Test Manufacturing mode
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//
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UINT32 DataPatternForMemoryTest[] = {
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0x55555555, 0xAAAAAAAA, 0x55555510, 0x555555EF, 0x55555510, 0x555555EF, 0x55555510, 0x555555EF,
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0x55555555, 0xAAAAAAAA, 0x55551055, 0x5555EF55, 0x55551055, 0x5555EF55, 0x55551055, 0x5555EF55,
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0x55555555, 0xAAAAAAAA, 0x55105555, 0x55EF5555, 0x55105555, 0x55EF5555, 0x55105555, 0x55EF5555,
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0x55555555, 0xAAAAAAAA, 0x10555555, 0xEF555555, 0x10555555, 0xEF555555, 0x10555555, 0xEF555555
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};
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#define DATA_PATTERN_ARRAY_SIZE (sizeof(DataPatternForMemoryTest) / sizeof(UINT32))
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//
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//Memory Test Manufacturing mode
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//
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//
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// The global indicator, the FvFileLoader callback will modify it to TRUE after loading PEIM into memory
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//
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BOOLEAN ImageInMemory = FALSE;
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EFI_STATUS
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EFIAPI
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Stall (
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IN CONST EFI_PEI_SERVICES **PeiServices,
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IN CONST EFI_PEI_STALL_PPI *This,
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IN UINTN Microseconds
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);
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EFI_STATUS
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EFIAPI
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MfgMemoryTest (
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IN CONST EFI_PEI_SERVICES **PeiServices,
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IN PEI_MFG_MEMORY_TEST_PPI *This,
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IN UINT32 BeginAddress,
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IN UINT32 MemoryLength
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);
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static EFI_PEI_STALL_PPI mStallPpi = {
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PEI_STALL_RESOLUTION,
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Stall
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};
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static PEI_MFG_MEMORY_TEST_PPI mPeiMfgMemoryTestPpi = {
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MfgMemoryTest
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};
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static EFI_PEI_PPI_DESCRIPTOR mInstallStallPpi[] = {
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{
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EFI_PEI_PPI_DESCRIPTOR_PPI,
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&gEfiPeiStallPpiGuid,
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&mStallPpi
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},
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{
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EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
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&gPeiMfgMemoryTestPpiGuid,
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&mPeiMfgMemoryTestPpi
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}
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};
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EFI_PEI_NOTIFY_DESCRIPTOR mMemoryDiscoveredNotifyList[1] = {
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{
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(EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
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&gEfiPeiMemoryDiscoveredPpiGuid,
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MemoryDiscoveredPpiNotifyCallback
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}
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};
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EFI_STATUS
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EFIAPI
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InstallMonoStatusCode (
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IN EFI_FFS_FILE_HEADER *FfsHeader,
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IN CONST EFI_PEI_SERVICES **PeiServices
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);
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EFI_STATUS
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ReadPlatformIds (
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IN CONST EFI_PEI_SERVICES **PeiServices,
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IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
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);
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//
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// Start::Alpine Valley platform
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//
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EFI_STATUS
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PeiSmbusExec (
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UINT16 SmbusBase,
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UINT8 SlvAddr,
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UINT8 Operation,
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UINT8 Offset,
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UINT8 *Length,
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UINT8 *Buffer
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);
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EFI_STATUS
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FtpmPolicyInit (
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IN CONST EFI_PEI_SERVICES **PeiServices,
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IN SYSTEM_CONFIGURATION *pSystemConfiguration
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)
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{
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EFI_STATUS Status;
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EFI_PEI_PPI_DESCRIPTOR *mFtpmPolicyPpiDesc;
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SEC_FTPM_POLICY_PPI *mFtpmPolicyPpi;
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DEBUG((EFI_D_INFO, "FtpmPolicyInit Entry \n"));
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if (NULL == PeiServices || NULL == pSystemConfiguration) {
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DEBUG((EFI_D_ERROR, "Input error. \n"));
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return EFI_INVALID_PARAMETER;
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}
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Status = (*PeiServices)->AllocatePool(
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PeiServices,
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sizeof (EFI_PEI_PPI_DESCRIPTOR),
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(void **)&mFtpmPolicyPpiDesc
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);
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ASSERT_EFI_ERROR (Status);
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Status = (*PeiServices)->AllocatePool(
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PeiServices,
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sizeof (SEC_FTPM_POLICY_PPI),
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(void **)&mFtpmPolicyPpi
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);
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ASSERT_EFI_ERROR (Status);
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//
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// Initialize PPI
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//
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(*PeiServices)->SetMem ((VOID *)mFtpmPolicyPpi, sizeof (SEC_FTPM_POLICY_PPI), 0);
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mFtpmPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
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mFtpmPolicyPpiDesc->Guid = &gSeCfTPMPolicyPpiGuid;
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mFtpmPolicyPpiDesc->Ppi = mFtpmPolicyPpi;
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DEBUG((EFI_D_INFO, "pSystemConfiguration->fTPM = 0x%x \n", pSystemConfiguration->fTPM));
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if(pSystemConfiguration->fTPM == 1) {
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mFtpmPolicyPpi->fTPMEnable = TRUE;
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} else {
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mFtpmPolicyPpi->fTPMEnable = FALSE;
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}
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Status = (*PeiServices)->InstallPpi(
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PeiServices,
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mFtpmPolicyPpiDesc
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);
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ASSERT_EFI_ERROR (Status);
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DEBUG((EFI_D_INFO, "FtpmPolicyInit done \n"));
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return EFI_SUCCESS;
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}
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/**
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This routine attempts to acquire the SMBus
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@retval FAILURE as failed
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@retval SUCCESS as passed
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**/
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EFI_STATUS
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AcquireBus (
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UINT16 SmbusBase
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)
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{
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UINT8 StsReg;
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StsReg = 0;
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StsReg = (UINT8)IoRead8(SmbusBase + R_PCH_SMBUS_HSTS);
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if (StsReg & B_PCH_SMBUS_IUS) {
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return EFI_DEVICE_ERROR;
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} else if (StsReg & B_PCH_SMBUS_HBSY) {
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//
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// Clear Status Register and exit
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//
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// Wait for HSTS.HBSY to be clear
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//
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do { StsReg = (UINT8) IoRead8(SmbusBase+R_PCH_SMBUS_HSTS); } while ((StsReg & B_PCH_SMBUS_HBSY) != 0);
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//
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// Clear all status bits
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//
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IoWrite8(SmbusBase+R_PCH_SMBUS_HSTS, 0xFE);
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return EFI_SUCCESS;
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} else {
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//
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// Clear out any odd status information (Will Not Clear In Use)
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//
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IoWrite8(SmbusBase+R_PCH_SMBUS_HSTS, StsReg);
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return EFI_SUCCESS;
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}
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}
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//
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// End::Alpine Valley platform
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//
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/**
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This function checks the memory range in PEI.
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@param PeiServices Pointer to PEI Services.
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@param This Pei memory test PPI pointer.
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@param BeginAddress Beginning of the memory address to be checked.
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@param MemoryLength Bytes of memory range to be checked.
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@param Operation Type of memory check operation to be performed.
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@param ErrorAddress Return the address of the error memory address.
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@retval EFI_SUCCESS The operation completed successfully.
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@retval EFI_DEVICE_ERROR Memory test failed. It's not safe to use this range of memory.
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**/
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EFI_STATUS
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EFIAPI
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MfgMemoryTest (
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IN CONST EFI_PEI_SERVICES **PeiServices,
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IN PEI_MFG_MEMORY_TEST_PPI *This,
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IN UINT32 BeginAddress,
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IN UINT32 MemoryLength
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)
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{
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UINT32 i;
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UINT32 memAddr;
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UINT32 readData;
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UINT32 xorData;
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UINT32 TestFlag = 0;
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memAddr = BeginAddress;
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//
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//Output Message for MFG
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//
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DEBUG ((EFI_D_ERROR, "MFGMODE SET\n"));
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//
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//Writting the pattern in defined location.
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//
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while (memAddr < (BeginAddress+MemoryLength)) {
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for (i = 0; i < DATA_PATTERN_ARRAY_SIZE; i++) {
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if (memAddr > (BeginAddress+MemoryLength -4)) {
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memAddr = memAddr + 4;
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break;
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}
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*((volatile UINT32*) memAddr) = DataPatternForMemoryTest[i];
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memAddr = memAddr + 4;
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}
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}
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//
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//Verify the pattern.
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//
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memAddr = BeginAddress;
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while (memAddr < (BeginAddress+MemoryLength)) {
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for (i = 0; i < DATA_PATTERN_ARRAY_SIZE; i++) {
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if (memAddr > (BeginAddress+MemoryLength -4)) {
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memAddr = memAddr + 4;
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break;
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}
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readData = *((volatile UINT32*) memAddr);
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xorData = readData ^ DataPatternForMemoryTest[i];
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//
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// If xorData is nonzero, this particular memAddr has a failure.
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//
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if (xorData != 0x00000000) {
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DEBUG ((EFI_D_ERROR, "Expected value....: %x\n", DataPatternForMemoryTest[i]));
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DEBUG ((EFI_D_ERROR, "ReadData value....: %x\n", readData));
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DEBUG ((EFI_D_ERROR, "Pattern failure at....: %x\n", memAddr));
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TestFlag = 1;
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}
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memAddr = memAddr + 4;
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}
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}
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if (TestFlag) {
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return EFI_DEVICE_ERROR;
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}
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//
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//Output Message for MFG
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//
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DEBUG ((EFI_D_ERROR, "MFGMODE MEMORY TEST PASSED\n"));
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return EFI_SUCCESS;
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}
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BOOLEAN
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IsRtcUipAlwaysSet (
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IN CONST EFI_PEI_SERVICES **PeiServices
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)
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{
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EFI_PEI_STALL_PPI *StallPpi;
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UINTN Count;
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(**PeiServices).LocatePpi (PeiServices, &gEfiPeiStallPpiGuid, 0, NULL, (void **)&StallPpi);
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for (Count = 0; Count < 500; Count++) { // Maximum waiting approximates to 1.5 seconds (= 3 msec * 500)
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IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_REGISTERA);
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if ((IoRead8 (R_PCH_RTC_TARGET2) & B_PCH_RTC_REGISTERA_UIP) == 0) {
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return FALSE;
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}
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StallPpi->Stall (PeiServices, StallPpi, 3000);
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}
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return TRUE;
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}
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EFI_STATUS
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RtcPowerFailureHandler (
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IN CONST EFI_PEI_SERVICES **PeiServices
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)
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{
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UINT16 DataUint16;
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UINT8 DataUint8;
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BOOLEAN RtcUipIsAlwaysSet;
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DataUint16 = MmioRead16 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1);
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RtcUipIsAlwaysSet = IsRtcUipAlwaysSet (PeiServices);
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if ((DataUint16 & B_PCH_PMC_GEN_PMCON_RTC_PWR_STS) || (RtcUipIsAlwaysSet)) {
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//
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// Execute the sequence below. This will ensure that the RTC state machine has been initialized.
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//
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// Step 1.
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// BIOS clears this bit by writing a '0' to it.
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//
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if (DataUint16 & B_PCH_PMC_GEN_PMCON_RTC_PWR_STS) {
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//
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// Set to invalid date in order to reset the time to
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// BIOS build time later in the boot (SBRUN.c file).
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//
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IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_YEAR);
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IoWrite8 (R_PCH_RTC_TARGET2, 0x0FF);
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IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_MONTH);
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IoWrite8 (R_PCH_RTC_TARGET2, 0x0FF);
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IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_DAYOFMONTH);
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IoWrite8 (R_PCH_RTC_TARGET2, 0x0FF);
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IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_DAYOFWEEK);
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IoWrite8 (R_PCH_RTC_TARGET2, 0x0FF);
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IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_SECONDSALARM);
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IoWrite8 (R_PCH_RTC_TARGET2, 0x00);
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IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_MINUTESALARM);
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IoWrite8 (R_PCH_RTC_TARGET2, 0x00);
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IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_HOURSALARM);
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IoWrite8 (R_PCH_RTC_TARGET2, 0x00);
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}
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//
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// Step 2.
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// Set RTC Register 0Ah[6:4] to '110' or '111'.
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//
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IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_REGISTERA);
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IoWrite8 (R_PCH_RTC_TARGET2, (V_PCH_RTC_REGISTERA_DV_DIV_RST1 | V_PCH_RTC_REGISTERA_RS_976P5US));
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//
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// Step 3.
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// Set RTC Register 0Bh[7].
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//
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IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_REGISTERB);
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DataUint8 = (IoRead8 (R_PCH_RTC_TARGET2) | B_PCH_RTC_REGISTERB_SET);
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IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_REGISTERB);
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IoWrite8 (R_PCH_RTC_TARGET2, DataUint8);
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//
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// Step 4.
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// Set RTC Register 0Ah[6:4] to '010'.
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//
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IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_REGISTERA);
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IoWrite8 (R_PCH_RTC_TARGET2, (V_PCH_RTC_REGISTERA_DV_NORM_OP | V_PCH_RTC_REGISTERA_RS_976P5US));
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//
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// Step 5.
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// Clear RTC Register 0Bh[7].
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//
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IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_REGISTERB);
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DataUint8 = (IoRead8 (R_PCH_RTC_TARGET2) & (UINT8)~B_PCH_RTC_REGISTERB_SET);
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IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_REGISTERB);
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IoWrite8 (R_PCH_RTC_TARGET2, DataUint8);
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}
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return EFI_SUCCESS;
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}
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VOID
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PchBaseInit (
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VOID
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)
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{
|
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//
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// Program ACPI Power Management I/O Space Base Address
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|
//
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|
MmioWrite16 (
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MmPciAddress (0,
|
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_LPC,
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PCI_FUNCTION_NUMBER_PCH_LPC,
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|
R_PCH_LPC_ACPI_BASE
|
|
),
|
|
(UINT16)((ACPI_BASE_ADDRESS & B_PCH_LPC_ACPI_BASE_BAR) | B_PCH_LPC_ACPI_BASE_EN)
|
|
);
|
|
|
|
//
|
|
// Program GPIO Base Address
|
|
//
|
|
MmioWrite16 (
|
|
MmPciAddress (0,
|
|
DEFAULT_PCI_BUS_NUMBER_PCH,
|
|
PCI_DEVICE_NUMBER_PCH_LPC,
|
|
PCI_FUNCTION_NUMBER_PCH_LPC,
|
|
R_PCH_LPC_GPIO_BASE
|
|
),
|
|
(UINT16)((GPIO_BASE_ADDRESS & B_PCH_LPC_GPIO_BASE_BAR) | B_PCH_LPC_GPIO_BASE_EN)
|
|
);
|
|
|
|
//
|
|
// Set PMC Base Address
|
|
//
|
|
MmioWrite32 (
|
|
MmPciAddress (0,
|
|
DEFAULT_PCI_BUS_NUMBER_PCH,
|
|
PCI_DEVICE_NUMBER_PCH_LPC,
|
|
PCI_FUNCTION_NUMBER_PCH_LPC,
|
|
R_PCH_LPC_PMC_BASE
|
|
),
|
|
(UINT32)((PMC_BASE_ADDRESS & B_PCH_LPC_PMC_BASE_BAR) | B_PCH_LPC_PMC_BASE_EN)
|
|
);
|
|
|
|
//
|
|
// Set IO Base Address
|
|
//
|
|
MmioWrite32 (
|
|
MmPciAddress (0,
|
|
DEFAULT_PCI_BUS_NUMBER_PCH,
|
|
PCI_DEVICE_NUMBER_PCH_LPC,
|
|
PCI_FUNCTION_NUMBER_PCH_LPC,
|
|
R_PCH_LPC_IO_BASE
|
|
),
|
|
(UINT32)((IO_BASE_ADDRESS & B_PCH_LPC_IO_BASE_BAR) | B_PCH_LPC_IO_BASE_EN)
|
|
);
|
|
|
|
//
|
|
// Set ILB Base Address
|
|
//
|
|
MmioWrite32 (
|
|
MmPciAddress (0,
|
|
DEFAULT_PCI_BUS_NUMBER_PCH,
|
|
PCI_DEVICE_NUMBER_PCH_LPC,
|
|
PCI_FUNCTION_NUMBER_PCH_LPC,
|
|
R_PCH_LPC_ILB_BASE
|
|
),
|
|
(UINT32)((ILB_BASE_ADDRESS & B_PCH_LPC_ILB_BASE_BAR) | B_PCH_LPC_ILB_BASE_EN)
|
|
);
|
|
|
|
//
|
|
// Set PUnit Base Address
|
|
//
|
|
MmioWrite32 (
|
|
MmPciAddress (0,
|
|
DEFAULT_PCI_BUS_NUMBER_PCH,
|
|
PCI_DEVICE_NUMBER_PCH_LPC,
|
|
PCI_FUNCTION_NUMBER_PCH_LPC,
|
|
R_PCH_LPC_PUNIT_BASE
|
|
),
|
|
(UINT32)((PUNIT_BASE_ADDRESS & B_PCH_LPC_PUNIT_BASE_BAR) | B_PCH_LPC_PUNIT_BASE_EN)
|
|
);
|
|
|
|
//
|
|
// Set SPI Base Address
|
|
//
|
|
MmioWrite32 (
|
|
MmPciAddress (0,
|
|
DEFAULT_PCI_BUS_NUMBER_PCH,
|
|
PCI_DEVICE_NUMBER_PCH_LPC,
|
|
PCI_FUNCTION_NUMBER_PCH_LPC,
|
|
R_PCH_LPC_SPI_BASE
|
|
),
|
|
(UINT32)((SPI_BASE_ADDRESS & B_PCH_LPC_SPI_BASE_BAR) | B_PCH_LPC_SPI_BASE_EN)
|
|
);
|
|
|
|
//
|
|
// Set Root Complex Base Address
|
|
//
|
|
MmioWrite32 (
|
|
MmPciAddress (0,
|
|
DEFAULT_PCI_BUS_NUMBER_PCH,
|
|
PCI_DEVICE_NUMBER_PCH_LPC,
|
|
PCI_FUNCTION_NUMBER_PCH_LPC,
|
|
R_PCH_LPC_RCBA
|
|
),
|
|
(UINT32)((RCBA_BASE_ADDRESS & B_PCH_LPC_RCBA_BAR) | B_PCH_LPC_RCBA_EN)
|
|
);
|
|
|
|
//
|
|
// Set MPHY Base Address
|
|
//
|
|
MmioWrite32 (
|
|
MmPciAddress (0,
|
|
DEFAULT_PCI_BUS_NUMBER_PCH,
|
|
PCI_DEVICE_NUMBER_PCH_LPC,
|
|
PCI_FUNCTION_NUMBER_PCH_LPC,
|
|
R_PCH_LPC_MPHY_BASE
|
|
),
|
|
(UINT32)((MPHY_BASE_ADDRESS & B_PCH_LPC_MPHY_BASE_BAR) | B_PCH_LPC_MPHY_BASE_EN)
|
|
);
|
|
MmioWrite16 (
|
|
MmPciAddress (0,
|
|
DEFAULT_PCI_BUS_NUMBER_PCH,
|
|
PCI_DEVICE_NUMBER_PCH_SMBUS,
|
|
PCI_FUNCTION_NUMBER_PCH_SMBUS,
|
|
R_PCH_SMBUS_BASE
|
|
),
|
|
(UINT16)(SMBUS_BASE_ADDRESS & B_PCH_SMBUS_BASE_BAR)
|
|
);
|
|
|
|
MmioOr8 (
|
|
MmPciAddress (0,
|
|
DEFAULT_PCI_BUS_NUMBER_PCH,
|
|
PCI_DEVICE_NUMBER_PCH_SMBUS,
|
|
PCI_FUNCTION_NUMBER_PCH_SMBUS,
|
|
R_PCH_SMBUS_PCICMD
|
|
),
|
|
B_PCH_SMBUS_PCICMD_IOSE
|
|
);
|
|
|
|
}
|
|
|
|
/**
|
|
This is the entrypoint of PEIM
|
|
|
|
@param FileHandle Handle of the file being invoked.
|
|
@param PeiServices Describes the list of possible PEI Services.
|
|
|
|
@retval EFI_SUCCESS if it completed successfully.
|
|
**/
|
|
EFI_STATUS
|
|
EFIAPI
|
|
PeiInitPlatform (
|
|
IN EFI_PEI_FILE_HANDLE FileHandle,
|
|
IN CONST EFI_PEI_SERVICES **PeiServices
|
|
)
|
|
{
|
|
UINTN SmbusRegBase;
|
|
EFI_PLATFORM_INFO_HOB PlatformInfo;
|
|
EFI_STATUS Status= EFI_SUCCESS;
|
|
EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable = NULL;
|
|
UINTN VariableSize;
|
|
SYSTEM_CONFIGURATION SystemConfiguration;
|
|
UINT32 GGC = 0;
|
|
|
|
EFI_PEI_PPI_DESCRIPTOR *mVlvMmioPolicyPpiDesc;
|
|
VLV_MMIO_POLICY_PPI *mVlvMmioPolicyPpi;
|
|
|
|
ZeroMem (&PlatformInfo, sizeof(PlatformInfo));
|
|
|
|
Status = InstallMonoStatusCode(FileHandle, PeiServices);
|
|
ASSERT_EFI_ERROR (Status);
|
|
|
|
|
|
//
|
|
// Initialize Stall PPIs
|
|
//
|
|
Status = (*PeiServices)->InstallPpi (PeiServices, &mInstallStallPpi[0]);
|
|
ASSERT_EFI_ERROR (Status);
|
|
|
|
Status = (*PeiServices)->NotifyPpi (PeiServices, &mMemoryDiscoveredNotifyList[0]);
|
|
ASSERT_EFI_ERROR (Status);
|
|
SmbusRegBase = PchPciDeviceMmBase (
|
|
DEFAULT_PCI_BUS_NUMBER_PCH,
|
|
PCI_DEVICE_NUMBER_PCH_SMBUS,
|
|
PCI_FUNCTION_NUMBER_PCH_SMBUS
|
|
);
|
|
//
|
|
// Since PEI has no PCI enumerator, set the BAR & I/O space enable ourselves
|
|
//
|
|
MmioAndThenOr32 (SmbusRegBase + R_PCH_SMBUS_BASE, B_PCH_SMBUS_BASE_BAR, SMBUS_BASE_ADDRESS);
|
|
|
|
MmioOr8 (SmbusRegBase + R_PCH_SMBUS_PCICMD, B_PCH_SMBUS_PCICMD_IOSE);
|
|
|
|
PchBaseInit();
|
|
|
|
//
|
|
//Todo: confirm if we need program 8254
|
|
//
|
|
// Setting 8254
|
|
// Program timer 1 as refresh timer
|
|
//
|
|
IoWrite8 (0x43, 0x54);
|
|
IoWrite8 (0x41, 0x12);
|
|
|
|
//
|
|
// RTC power failure handling
|
|
//
|
|
RtcPowerFailureHandler (PeiServices);
|
|
|
|
|
|
PchMmPci32( 0, 0, 2, 0, 0x50) = 0x210;
|
|
|
|
VariableSize = sizeof (SYSTEM_CONFIGURATION);
|
|
ZeroMem (&SystemConfiguration, VariableSize);
|
|
|
|
//
|
|
// Obtain variable services
|
|
//
|
|
Status = (*PeiServices)->LocatePpi(
|
|
PeiServices,
|
|
&gEfiPeiReadOnlyVariable2PpiGuid,
|
|
0,
|
|
NULL,
|
|
(void **)&Variable
|
|
);
|
|
ASSERT_EFI_ERROR(Status);
|
|
Status = Variable->GetVariable (
|
|
Variable,
|
|
L"Setup",
|
|
&gEfiSetupVariableGuid,
|
|
NULL,
|
|
&VariableSize,
|
|
&SystemConfiguration
|
|
);
|
|
if (EFI_ERROR (Status) || VariableSize != sizeof(SYSTEM_CONFIGURATION)) {
|
|
//The setup variable is corrupted
|
|
VariableSize = sizeof(SYSTEM_CONFIGURATION);
|
|
Status = Variable->GetVariable(
|
|
Variable,
|
|
L"SetupRecovery",
|
|
&gEfiSetupVariableGuid,
|
|
NULL,
|
|
&VariableSize,
|
|
&SystemConfiguration
|
|
);
|
|
ASSERT_EFI_ERROR (Status);
|
|
}
|
|
|
|
if (EFI_ERROR (Status)) {
|
|
GGC = ((2 << 3) | 0x200);
|
|
PciCfg16Write(EC_BASE, 0, 2, 0, 0x50, GGC);
|
|
GGC = PciCfg16Read(EC_BASE, 0, 2, 0, 0x50);
|
|
DEBUG((EFI_D_INFO , "GGC: 0x%08x GMSsize:0x%08x\n", GGC, (GGC & (BIT7|BIT6|BIT5|BIT4|BIT3))>>3));
|
|
} else {
|
|
if (SystemConfiguration.Igd == 1 && SystemConfiguration.PrimaryVideoAdaptor != 2) {
|
|
GGC = (SystemConfiguration.IgdDvmt50PreAlloc << 3) |
|
|
(SystemConfiguration.GTTSize == GTT_SIZE_1MB ? 0x100: 0x200);
|
|
PciCfg16Write(EC_BASE, 0, 2, 0, 0x50, GGC);
|
|
GGC = PciCfg16Read(EC_BASE, 0, 2, 0, 0x50);
|
|
DEBUG((EFI_D_INFO , "GGC: 0x%08x GMSsize:0x%08x\n", GGC, (GGC & (BIT7|BIT6|BIT5|BIT4|BIT3))>>3));
|
|
}
|
|
}
|
|
|
|
//
|
|
// Initialize PlatformInfo HOB
|
|
//
|
|
Status = ReadPlatformIds(PeiServices, &PlatformInfo);
|
|
ASSERT_EFI_ERROR (Status);
|
|
|
|
//
|
|
// 0 -> Disable , 1 -> Enable
|
|
//
|
|
if(SystemConfiguration.CfioPnpSettings == 1) {
|
|
DEBUG((EFI_D_INFO, "CheckCfioPnpSettings: CFIO Pnp Settings Enabled\n"));
|
|
PlatformInfo.CfioEnabled = 1;
|
|
} else {
|
|
DEBUG((EFI_D_INFO, "CheckCfioPnpSettings: CFIO Pnp Settings Disabled\n"));
|
|
PlatformInfo.CfioEnabled = 0;
|
|
}
|
|
|
|
//
|
|
// Build HOB for PlatformInfo
|
|
//
|
|
BuildGuidDataHob (
|
|
&gEfiPlatformInfoGuid,
|
|
&PlatformInfo,
|
|
sizeof (EFI_PLATFORM_INFO_HOB)
|
|
);
|
|
|
|
|
|
#ifdef FTPM_ENABLE
|
|
Status = FtpmPolicyInit(PeiServices, &SystemConfiguration);
|
|
if (EFI_ERROR (Status)) {
|
|
DEBUG((EFI_D_ERROR, "fTPM init failed.\n"));
|
|
}
|
|
#endif
|
|
|
|
|
|
//
|
|
// Set the new boot mode for MRC
|
|
//
|
|
#ifdef NOCS_S3_SUPPORT
|
|
Status = UpdateBootMode (PeiServices);
|
|
ASSERT_EFI_ERROR (Status);
|
|
#endif
|
|
|
|
DEBUG((EFI_D_INFO, "Setup MMIO size ... \n\n"));
|
|
|
|
//
|
|
// Setup MMIO size
|
|
//
|
|
Status = (*PeiServices)->AllocatePool(
|
|
PeiServices,
|
|
sizeof (EFI_PEI_PPI_DESCRIPTOR),
|
|
(void **)&mVlvMmioPolicyPpiDesc
|
|
);
|
|
ASSERT_EFI_ERROR (Status);
|
|
Status = (*PeiServices)->AllocatePool(
|
|
PeiServices,
|
|
sizeof (VLV_MMIO_POLICY_PPI),
|
|
(void **)&mVlvMmioPolicyPpi
|
|
);
|
|
ASSERT_EFI_ERROR (Status);
|
|
(*PeiServices)->SetMem (
|
|
(VOID *)mVlvMmioPolicyPpi,
|
|
sizeof (VLV_MMIO_POLICY_PPI),
|
|
0
|
|
);
|
|
mVlvMmioPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
|
|
mVlvMmioPolicyPpiDesc->Guid = &gVlvMmioPolicyPpiGuid;
|
|
mVlvMmioPolicyPpiDesc->Ppi = mVlvMmioPolicyPpi;
|
|
switch (SystemConfiguration.MmioSize) {
|
|
case 0: // 768MB
|
|
mVlvMmioPolicyPpi->MmioSize = 0x300;
|
|
break;
|
|
case 1: // 1GB
|
|
mVlvMmioPolicyPpi->MmioSize = 0x400;
|
|
break;
|
|
case 2: // 1.25GB
|
|
mVlvMmioPolicyPpi->MmioSize = 0x500;
|
|
break;
|
|
case 3: // 1.5GB
|
|
mVlvMmioPolicyPpi->MmioSize = 0x600;
|
|
break;
|
|
case 4: // 2GB
|
|
mVlvMmioPolicyPpi->MmioSize = 0x800;
|
|
break;
|
|
default:
|
|
mVlvMmioPolicyPpi->MmioSize = 0x800;
|
|
break;
|
|
}
|
|
Status = (*PeiServices)->InstallPpi(
|
|
PeiServices,
|
|
mVlvMmioPolicyPpiDesc
|
|
);
|
|
ASSERT_EFI_ERROR (Status);
|
|
|
|
return Status;
|
|
}
|
|
|
|
EFI_STATUS
|
|
ReadPlatformIds (
|
|
IN CONST EFI_PEI_SERVICES **PeiServices,
|
|
IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
|
|
)
|
|
{
|
|
{
|
|
EFI_STATUS Status = EFI_SUCCESS;
|
|
UINT8 FabId = 0;
|
|
UINTN DataSize;
|
|
EFI_PLATFORM_INFO_HOB TmpHob;
|
|
EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiVar;
|
|
|
|
Status = (**PeiServices).LocatePpi (
|
|
PeiServices,
|
|
&gEfiPeiReadOnlyVariable2PpiGuid,
|
|
0,
|
|
NULL,
|
|
(void **)&PeiVar
|
|
);
|
|
ASSERT_EFI_ERROR (Status);
|
|
|
|
DataSize = sizeof (EFI_PLATFORM_INFO_HOB);
|
|
Status = PeiVar->GetVariable (
|
|
PeiVar,
|
|
L"PlatformInfo",
|
|
&gEfiVlv2VariableGuid,
|
|
NULL,
|
|
&DataSize,
|
|
&TmpHob
|
|
);
|
|
|
|
if (Status == EFI_SUCCESS) {
|
|
PlatformInfoHob->BoardId = TmpHob.BoardId;
|
|
PlatformInfoHob->MemCfgID = TmpHob.MemCfgID;
|
|
PlatformInfoHob->BoardRev = TmpHob.BoardRev;
|
|
PlatformInfoHob->PlatformFlavor = TmpHob.PlatformFlavor;
|
|
return Status;
|
|
}
|
|
|
|
|
|
PlatformInfoHob->BoardId = BOARD_ID_MINNOW2;
|
|
DEBUG ((EFI_D_INFO, "I'm Minnow2!\n"));
|
|
|
|
PlatformInfoHob->MemCfgID = 0;
|
|
PlatformInfoHob->BoardRev = FabId + 1; // FabId = 0 means FAB1 (BoardRev = 1), FabId = 1 means FAB2 (BoardRev = 2)...
|
|
PlatformInfoHob->PlatformFlavor = FlavorMobile;
|
|
}
|
|
|
|
return EFI_SUCCESS;
|
|
}
|
|
|
|
//
|
|
// Start::Alpine Valley platform
|
|
//
|
|
/**
|
|
This routine reads SysCtl registers
|
|
|
|
@param SmbusBase SMBUS Base Address
|
|
@param SlvAddr Targeted Smbus Slave device address
|
|
@param Operation Which SMBus protocol will be used
|
|
@param Offset Offset of the register
|
|
@param Length Number of bytes
|
|
@param Buffer Buffer contains values read from registers
|
|
|
|
@retval SUCCESS as passed
|
|
@retval Others as failed
|
|
|
|
**/
|
|
EFI_STATUS
|
|
PeiSmbusExec (
|
|
UINT16 SmbusBase,
|
|
UINT8 SlvAddr,
|
|
UINT8 Operation,
|
|
UINT8 Offset,
|
|
UINT8 *Length,
|
|
UINT8 *Buffer
|
|
)
|
|
{
|
|
EFI_STATUS Status=EFI_SUCCESS;
|
|
UINT8 AuxcReg;
|
|
UINT8 SmbusOperation = 0;
|
|
UINT8 StsReg;
|
|
UINT8 SlvAddrReg;
|
|
UINT8 HostCmdReg;
|
|
UINT8 BlockCount = 0;
|
|
BOOLEAN BufferTooSmall;
|
|
UINT8 Index;
|
|
UINT8 *CallBuffer;
|
|
UINT8 RetryCount = BUS_TRIES;
|
|
|
|
//
|
|
// MrcSmbusExec supports byte and block read.
|
|
// Only allow Byte or block access
|
|
//
|
|
if (!((*Length == AV_SC_BYTE_LEN) || (*Length == AV_SC_BLOCK_LEN))) {
|
|
return EFI_INVALID_PARAMETER;
|
|
}
|
|
|
|
//
|
|
// See if its ok to use the bus based upon INUSE_STS bit.
|
|
//
|
|
Status = AcquireBus (SmbusBase);
|
|
ASSERT_EFI_ERROR(Status);
|
|
|
|
CallBuffer = Buffer;
|
|
|
|
//
|
|
//SmbStatus Bits of interest
|
|
//[6] = IUS (In Use Status)
|
|
//[4] = FAIL
|
|
//[3] = BERR (Bus Error = transaction collision)
|
|
//[2] = DERR (Device Error = Illegal Command Field, Unclaimed Cycle, Host Device Timeout, CRC Error)
|
|
//[1] = INTR (Successful completion of last command)
|
|
//[0] = HOST BUSY
|
|
//
|
|
//
|
|
// This is the main operation loop. If the operation results in a Smbus
|
|
// collision with another master on the bus, it attempts the requested
|
|
// transaction again at least BUS_TRIES attempts.
|
|
//
|
|
while (RetryCount--) {
|
|
//
|
|
// Operation Specifics (pre-execution)
|
|
//
|
|
Status = EFI_SUCCESS;
|
|
SlvAddrReg = SlvAddr;
|
|
HostCmdReg = Offset;
|
|
AuxcReg = 0;
|
|
|
|
switch (Operation) {
|
|
|
|
case SMBUS_WRITE_BYTE:
|
|
IoWrite8 (SmbusBase+R_PCH_SMBUS_HD0, CallBuffer[0]);
|
|
SmbusOperation = V_PCH_SMBUS_SMB_CMD_BYTE_DATA;
|
|
break;
|
|
|
|
case SMBUS_READ_BYTE:
|
|
SmbusOperation = V_PCH_SMBUS_SMB_CMD_BYTE_DATA;
|
|
SlvAddrReg |= B_PCH_SMBUS_RW_SEL_READ;
|
|
if (*Length < 1) {
|
|
Status = EFI_INVALID_PARAMETER;
|
|
}
|
|
*Length = 1;
|
|
break;
|
|
|
|
case SMBUS_WRITE_BLOCK:
|
|
SmbusOperation = V_PCH_SMBUS_SMB_CMD_BLOCK;
|
|
IoWrite8 (SmbusBase+R_PCH_SMBUS_HD0, *(UINT8 *) Length);
|
|
BlockCount = (UINT8) (*Length);
|
|
if ((*Length < 1) || (*Length > 32)) {
|
|
Status = EFI_INVALID_PARAMETER;
|
|
break;
|
|
}
|
|
AuxcReg |= B_PCH_SMBUS_E32B;
|
|
break;
|
|
|
|
case SMBUS_READ_BLOCK:
|
|
SmbusOperation = V_PCH_SMBUS_SMB_CMD_BLOCK;
|
|
SlvAddrReg |= B_PCH_SMBUS_RW_SEL_READ;
|
|
if ((*Length < 1) || (*Length > 32)) {
|
|
Status = EFI_INVALID_PARAMETER;
|
|
break;
|
|
}
|
|
AuxcReg |= B_PCH_SMBUS_E32B;
|
|
break;
|
|
|
|
default:
|
|
Status = EFI_INVALID_PARAMETER;
|
|
break;
|
|
}
|
|
|
|
//
|
|
// Set Auxiliary Control register
|
|
//
|
|
IoWrite8 (SmbusBase+R_PCH_SMBUS_AUXC, AuxcReg);
|
|
|
|
//
|
|
// Reset the pointer of the internal buffer
|
|
//
|
|
IoRead8 (SmbusBase+R_PCH_SMBUS_HCTL);
|
|
|
|
//
|
|
// Now that the 32 byte buffer is turned on, we can write th block data
|
|
// into it
|
|
//
|
|
if (Operation == SMBUS_WRITE_BLOCK) {
|
|
for (Index = 0; Index < BlockCount; Index++) {
|
|
//
|
|
// Write next byte
|
|
//
|
|
IoWrite8 (SmbusBase+R_PCH_SMBUS_HBD, CallBuffer[Index]);
|
|
}
|
|
}
|
|
|
|
//
|
|
// Set SMBus slave address for the device to read
|
|
//
|
|
IoWrite8(SmbusBase+R_PCH_SMBUS_TSA, SlvAddrReg);
|
|
|
|
//
|
|
//
|
|
// Set Command register for the offset to read
|
|
//
|
|
IoWrite8(SmbusBase+R_PCH_SMBUS_HCMD, HostCmdReg );
|
|
|
|
//
|
|
// Set Control Register to Set "operation command" protocol and start bit
|
|
//
|
|
IoWrite8(SmbusBase+R_PCH_SMBUS_HCTL, (UINT8) (SmbusOperation + B_PCH_SMBUS_START));
|
|
|
|
//
|
|
// Wait for IO to complete
|
|
//
|
|
do { StsReg = (UINT8) IoRead8(SmbusBase+0); } while ((StsReg & (BIT4|BIT3|BIT2|BIT1)) == 0);
|
|
|
|
if (StsReg & B_PCH_SMBUS_DERR) {
|
|
Status = EFI_DEVICE_ERROR;
|
|
break;
|
|
} else if (StsReg & B_PCH_SMBUS_BERR) {
|
|
//
|
|
// Clear the Bus Error for another try
|
|
//
|
|
Status = EFI_DEVICE_ERROR;
|
|
IoWrite8(SmbusBase+R_PCH_SMBUS_HSTS, B_PCH_SMBUS_BERR);
|
|
|
|
//
|
|
// Clear Status Registers
|
|
//
|
|
IoWrite8(SmbusBase+R_PCH_SMBUS_HSTS, B_PCH_SMBUS_HSTS_ALL);
|
|
IoWrite8(SmbusBase+R_PCH_SMBUS_AUXS, B_PCH_SMBUS_CRCE);
|
|
|
|
continue;
|
|
}
|
|
|
|
//
|
|
// successfull completion
|
|
// Operation Specifics (post-execution)
|
|
//
|
|
switch (Operation) {
|
|
|
|
case SMBUS_READ_BYTE:
|
|
CallBuffer[0] = (UINT8)(IoRead8 (SmbusBase+R_PCH_SMBUS_HD0));
|
|
break;
|
|
|
|
case SMBUS_WRITE_BLOCK:
|
|
IoWrite8(SmbusBase+R_PCH_SMBUS_HSTS, B_PCH_SMBUS_BYTE_DONE_STS);
|
|
break;
|
|
|
|
case SMBUS_READ_BLOCK:
|
|
BufferTooSmall = FALSE;
|
|
|
|
//
|
|
// Find out how many bytes will be in the block
|
|
//
|
|
BlockCount = (UINT8)(IoRead8 (SmbusBase+R_PCH_SMBUS_HD0));
|
|
if (*Length < BlockCount) {
|
|
BufferTooSmall = TRUE;
|
|
} else {
|
|
for (Index = 0; Index < BlockCount; Index++) {
|
|
//
|
|
// Read the byte
|
|
//
|
|
CallBuffer[Index] = (UINT8)IoRead8 (SmbusBase+R_PCH_SMBUS_HBD);
|
|
}
|
|
}
|
|
|
|
*Length = BlockCount;
|
|
if (BufferTooSmall) {
|
|
Status = EFI_BUFFER_TOO_SMALL;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
};
|
|
|
|
if ((StsReg & B_PCH_SMBUS_BERR) && (Status == EFI_SUCCESS)) {
|
|
//
|
|
// Clear the Bus Error for another try
|
|
//
|
|
Status = EFI_DEVICE_ERROR;
|
|
IoWrite8(SmbusBase+R_PCH_SMBUS_HSTS, B_PCH_SMBUS_BERR);
|
|
|
|
continue;
|
|
} else {
|
|
break;
|
|
}
|
|
}
|
|
|
|
//
|
|
// Clear Status Registers and exit
|
|
//
|
|
IoWrite8(SmbusBase+R_PCH_SMBUS_HSTS, B_PCH_SMBUS_HSTS_ALL);
|
|
IoWrite8(SmbusBase+R_PCH_SMBUS_AUXS, B_PCH_SMBUS_CRCE);
|
|
IoWrite8(SmbusBase+R_PCH_SMBUS_AUXC, 0);
|
|
return Status;
|
|
}
|
|
//
|
|
// End::Alpine Valley platform
|
|
//
|
|
|