mirror of https://github.com/acidanthera/audk.git
105 lines
2.8 KiB
C
105 lines
2.8 KiB
C
/** @file
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Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _FSP_GLOBAL_DATA_H_
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#define _FSP_GLOBAL_DATA_H_
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#include <FspEas.h>
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#define FSP_IN_API_MODE 0
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#define FSP_IN_DISPATCH_MODE 1
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#define FSP_GLOBAL_DATA_VERSION 0x3
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#pragma pack(1)
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typedef enum {
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TempRamInitApiIndex,
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FspInitApiIndex,
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NotifyPhaseApiIndex,
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FspMemoryInitApiIndex,
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TempRamExitApiIndex,
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FspSiliconInitApiIndex,
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FspMultiPhaseSiInitApiIndex,
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FspSmmInitApiIndex,
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FspMultiPhaseMemInitApiIndex,
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FspApiIndexMax
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} FSP_API_INDEX;
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typedef struct {
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VOID *DataPtr;
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UINTN MicrocodeRegionBase;
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UINTN MicrocodeRegionSize;
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UINTN CodeRegionBase;
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UINTN CodeRegionSize;
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UINTN Reserved;
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} FSP_PLAT_DATA;
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#define FSP_GLOBAL_DATA_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'D')
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#define FSP_PERFORMANCE_DATA_SIGNATURE SIGNATURE_32 ('P', 'E', 'R', 'F')
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#define FSP_PERFORMANCE_DATA_TIMER_MASK 0xFFFFFFFFFFFFFF
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typedef struct {
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UINT32 Signature;
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UINT8 Version;
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UINT8 Reserved1[3];
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///
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/// Offset 0x08
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///
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UINTN CoreStack;
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VOID *SmmInitUpdPtr;
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///
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/// IA32: Offset 0x10; X64: Offset 0x18
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///
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UINT32 StatusCode;
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UINT8 ApiIdx;
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///
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/// 0: FSP in API mode; 1: FSP in DISPATCH mode
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///
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UINT8 FspMode;
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UINT8 OnSeparateStack;
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UINT8 Reserved2;
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UINT32 NumberOfPhases;
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UINT32 PhasesExecuted;
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UINT32 Reserved3[8];
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///
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/// IA32: Offset 0x40; X64: Offset 0x48
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/// Start of UINTN and pointer section
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/// All UINTN and pointer members are put in this section
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/// for maintaining natural alignment for both IA32 and X64 builds.
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///
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FSP_PLAT_DATA PlatformData;
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VOID *TempRamInitUpdPtr;
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VOID *MemoryInitUpdPtr;
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VOID *SiliconInitUpdPtr;
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///
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/// IA32: Offset 0x64; X64: Offset 0x90
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/// To store function parameters pointer
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/// so it can be retrieved after stack switched.
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///
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VOID *FunctionParameterPtr;
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FSP_INFO_HEADER *FspInfoHeader;
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VOID *UpdDataPtr;
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VOID *FspHobListPtr;
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VOID *VariableRequestParameterPtr;
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///
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/// End of UINTN and pointer section
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/// At this point, next field offset must be either *0h or *8h to
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/// meet natural alignment requirement.
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///
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UINT8 Reserved4[16];
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UINT32 PerfSig;
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UINT16 PerfLen;
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UINT16 Reserved5;
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UINT32 PerfIdx;
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UINT32 Reserved6;
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UINT64 PerfData[32];
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} FSP_GLOBAL_DATA;
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#pragma pack()
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#endif
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