mirror of https://github.com/acidanthera/audk.git
130 lines
3.1 KiB
ArmAsm
130 lines
3.1 KiB
ArmAsm
#------------------------------------------------------------------------------
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#
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# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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#include <AsmMacroIoLibV8.h>
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.text
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.align 3
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GCC_ASM_EXPORT (ArmIsMpCore)
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GCC_ASM_EXPORT (ArmEnableAsynchronousAbort)
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GCC_ASM_EXPORT (ArmDisableAsynchronousAbort)
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GCC_ASM_EXPORT (ArmEnableIrq)
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GCC_ASM_EXPORT (ArmDisableIrq)
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GCC_ASM_EXPORT (ArmEnableFiq)
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GCC_ASM_EXPORT (ArmDisableFiq)
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GCC_ASM_EXPORT (ArmEnableInterrupts)
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GCC_ASM_EXPORT (ArmDisableInterrupts)
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GCC_ASM_EXPORT (ArmDisableAllExceptions)
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GCC_ASM_EXPORT (ReadCCSIDR)
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GCC_ASM_EXPORT (ReadCLIDR)
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#------------------------------------------------------------------------------
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.set MPIDR_U_BIT, (30)
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.set MPIDR_U_MASK, (1 << MPIDR_U_BIT)
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// DAIF bit definitions for writing through msr daifclr/sr daifset
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.set DAIF_WR_FIQ_BIT, (1 << 0)
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.set DAIF_WR_IRQ_BIT, (1 << 1)
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.set DAIF_WR_ABORT_BIT, (1 << 2)
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.set DAIF_WR_DEBUG_BIT, (1 << 3)
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.set DAIF_WR_INT_BITS, (DAIF_WR_FIQ_BIT | DAIF_WR_IRQ_BIT)
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.set DAIF_WR_ALL, (DAIF_WR_DEBUG_BIT | DAIF_WR_ABORT_BIT | DAIF_WR_INT_BITS)
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ASM_PFX(ArmIsMpCore):
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mrs x0, mpidr_el1 // Read EL1 Mutliprocessor Affinty Reg (MPIDR)
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and x0, x0, #MPIDR_U_MASK // U Bit clear, the processor is part of a multiprocessor system
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lsr x0, x0, #MPIDR_U_BIT
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eor x0, x0, #1
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ret
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ASM_PFX(ArmEnableAsynchronousAbort):
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msr daifclr, #DAIF_WR_ABORT_BIT
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isb
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ret
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ASM_PFX(ArmDisableAsynchronousAbort):
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msr daifset, #DAIF_WR_ABORT_BIT
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isb
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ret
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ASM_PFX(ArmEnableIrq):
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msr daifclr, #DAIF_WR_IRQ_BIT
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isb
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ret
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ASM_PFX(ArmDisableIrq):
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msr daifset, #DAIF_WR_IRQ_BIT
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isb
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ret
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ASM_PFX(ArmEnableFiq):
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msr daifclr, #DAIF_WR_FIQ_BIT
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isb
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ret
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ASM_PFX(ArmDisableFiq):
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msr daifset, #DAIF_WR_FIQ_BIT
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isb
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ret
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ASM_PFX(ArmEnableInterrupts):
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msr daifclr, #DAIF_WR_INT_BITS
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isb
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ret
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ASM_PFX(ArmDisableInterrupts):
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msr daifset, #DAIF_WR_INT_BITS
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isb
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ret
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ASM_PFX(ArmDisableAllExceptions):
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msr daifset, #DAIF_WR_ALL
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isb
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ret
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// UINT32
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// ReadCCSIDR (
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// IN UINT32 CSSELR
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// )
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ASM_PFX(ReadCCSIDR):
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msr csselr_el1, x0 // Write Cache Size Selection Register (CSSELR)
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isb
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mrs x0, ccsidr_el1 // Read current Cache Size ID Register (CCSIDR)
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ret
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// UINT32
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// ReadCLIDR (
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// IN UINT32 CSSELR
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// )
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ASM_PFX(ReadCLIDR):
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mrs x0, clidr_el1 // Read Cache Level ID Register
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ret
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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