mirror of https://github.com/acidanthera/audk.git
90 lines
4.2 KiB
Plaintext
90 lines
4.2 KiB
Plaintext
/** @file
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FACP Table
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Copyright (c) 2013, Red Hat, Inc.
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Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "Platform.h"
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EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = {
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{
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EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
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sizeof (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE),
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EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
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0, // to make sum of entire table == 0
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{EFI_ACPI_OEM_ID}, // OEMID is a 6 bytes long field
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EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long)
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EFI_ACPI_OEM_REVISION, // OEM revision number
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EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID
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EFI_ACPI_CREATOR_REVISION // ASL compiler revision number
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},
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0, // Physical address of FACS
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0, // Physical address of DSDT
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RESERVED, // System Interrupt Model in ACPI 1.0, eliminated in 2.0
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EFI_ACPI_2_0_PM_PROFILE_UNSPECIFIED, // Preferred PM profile
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SCI_INT_VECTOR, // System vector of SCI interrupt
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SMI_CMD_IO_PORT, // Port address of SMI command port
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ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI
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ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI
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S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state
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0, // PState control
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PM1a_EVT_BLK, // Port address of Power Mgt 1a Event Reg Blk
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0, // Power Mgt 1b Event Reg Blk unsupported
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PM1a_CNT_BLK, // Port address of Power Mgt 1a Ctrl Reg Blk
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0, // Power Mgt 1b Ctrl Reg Blk unsupported
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0, // Power Mgt 2 Ctrl Reg Blk unsupported
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PM_TMR_BLK, // Port address of Power Mgt Timer Ctrl Reg Blk
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GPE0_BLK, // Port addr of General Purpose Event 0 Reg Blk
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0, // General Purpose Event 1 Reg Blk unsupported
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PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk
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PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk
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0, // Power Mgt 2 Ctrl Reg Blk unsupported
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PM_TM_LEN, // Byte Length of ports at pm_tm_blk
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GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk
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0, // General Purpose Event 1 Reg Blk unsupported
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0, // General Purpose Event 1 Reg Blk unsupported
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0, // _CST support
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P_LVL2_LAT, // worst case HW latency to enter/exit C2 state
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P_LVL3_LAT, // worst case HW latency to enter/exit C3 state
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FLUSH_SIZE, // Size of area read to flush caches
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FLUSH_STRIDE, // Stride used in flushing caches
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DUTY_OFFSET, // bit location of duty cycle field in p_cnt reg
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DUTY_WIDTH, // bit width of duty cycle field in p_cnt reg
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DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM
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MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM
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CENTURY, // index to century in RTC CMOS RAM
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0x0000, // Boot architecture flag (16-bit)
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RESERVED, // reserved
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FLAG, // Fixed feature flags
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GAS2_IO(RESET_REG, 1), // Extended address of the Reset Register
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RESET_VALUE, // Value for the Reset Register to reset the system
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{ RESERVED }, // reserved[3]
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0, // 64-bit physical address of FACS, set at installation
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0, // 64-bit physical address of DSDT, set at installation
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GAS2_IO(PM1a_EVT_BLK, PM1_EVT_LEN), // Ext. addr. of PM 1a Event Reg Blk
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{ 0 }, // PM 1b Event Reg Blk unsupported
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GAS2_IO(PM1a_CNT_BLK, PM1_CNT_LEN), // Ext. addr. of PM 1a Ctrl Reg Blk
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{ 0 }, // PM 1b Ctrl Reg Blk unsupported
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{ 0 }, // PM 2 Ctrl Reg Blk unsupported
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GAS2_IO(PM_TMR_BLK, PM_TM_LEN), // Ext. addr. of PM Timer Ctrl Reg Blk
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GAS2_IO(GPE0_BLK, GPE0_BLK_LEN), // Ext. addr. of GPE 0 Reg Blk
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{ 0 } // GPE 1 Reg Blk unsupported
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};
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VOID*
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ReferenceAcpiTable (
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VOID
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)
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{
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//
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// Reference the table being generated to prevent the optimizer from removing the
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// data structure from the executable
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//
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return (VOID*)&FACP;
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}
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