mirror of https://github.com/acidanthera/audk.git
131 lines
3.5 KiB
C
131 lines
3.5 KiB
C
/** @file
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Provide constructor and GetTick for BaseRom instance of ACPI Timer Library
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Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.
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Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
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This program and the accompanying materials are licensed and made
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available under the terms and conditions of the BSD License which
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accompanies this distribution. The full text of the license may
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be found at http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/PciLib.h>
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#include <Library/PcdLib.h>
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#include <OvmfPlatforms.h>
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//
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// Power Management PCI Configuration Register fields
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//
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#define PMBA_RTE BIT0
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#define PMIOSE BIT0
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//
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// Offset in the Power Management Base Address to the ACPI Timer
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//
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#define ACPI_TIMER_OFFSET 0x8
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/**
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The constructor function enables ACPI IO space.
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If ACPI I/O space not enabled, this function will enable it.
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It will always return RETURN_SUCCESS.
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@retval EFI_SUCCESS The constructor always returns RETURN_SUCCESS.
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**/
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RETURN_STATUS
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EFIAPI
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AcpiTimerLibConstructor (
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VOID
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)
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{
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UINT16 HostBridgeDevId;
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UINTN Pmba;
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UINTN PmRegMisc;
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//
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// Query Host Bridge DID to determine platform type
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//
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HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
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switch (HostBridgeDevId) {
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case INTEL_82441_DEVICE_ID:
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Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);
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PmRegMisc = POWER_MGMT_REGISTER_PIIX4 (0x80);
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break;
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case INTEL_Q35_MCH_DEVICE_ID:
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Pmba = POWER_MGMT_REGISTER_Q35 (0x40);
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PmRegMisc = POWER_MGMT_REGISTER_Q35 (0x80);
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break;
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default:
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DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
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__FUNCTION__, HostBridgeDevId));
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ASSERT (FALSE);
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return RETURN_UNSUPPORTED;
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}
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//
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// Check to see if the Power Management Base Address is already enabled
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//
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if ((PciRead8 (PmRegMisc) & PMIOSE) == 0) {
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//
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// If the Power Management Base Address is not programmed,
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// then program the Power Management Base Address from a PCD.
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//
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PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));
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//
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// Enable PMBA I/O port decodes in PMREGMISC
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//
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PciOr8 (PmRegMisc, PMIOSE);
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}
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return RETURN_SUCCESS;
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}
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/**
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Internal function to read the current tick counter of ACPI.
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Dynamically compute the address of the ACPI tick counter based on the
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properties of the underlying platform, to avoid relying on global variables.
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@return The tick counter read.
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**/
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UINT32
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InternalAcpiGetTimerTick (
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VOID
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)
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{
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UINT16 HostBridgeDevId;
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UINTN Pmba;
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//
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// Query Host Bridge DID to determine platform type
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//
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HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
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switch (HostBridgeDevId) {
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case INTEL_82441_DEVICE_ID:
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Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);
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break;
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case INTEL_Q35_MCH_DEVICE_ID:
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Pmba = POWER_MGMT_REGISTER_Q35 (0x40);
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break;
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default:
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DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
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__FUNCTION__, HostBridgeDevId));
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ASSERT (FALSE);
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return 0;
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}
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//
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// Read PMBA to read and return the current ACPI timer value.
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//
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return IoRead32 ((PciRead32 (Pmba) & ~PMBA_RTE) + ACPI_TIMER_OFFSET);
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}
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