mirror of https://github.com/acidanthera/audk.git
106 lines
4.0 KiB
C
106 lines
4.0 KiB
C
/** @file
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Include file for PC-AT compatability.
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Copyright (c) 2006, Intel Corporation. All rights reserved.
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This software and associated documentation (if any) is furnished
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under a license and may only be used or copied in accordance
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with the terms of the license. Except as permitted by such
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license, no part of this software or documentation may be
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reproduced, stored in a retrieval system, or transmitted in any
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form or by any means without the express written consent of
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Intel Corporation.
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**/
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#ifndef _PC_AT_H_
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#define _PC_AT_H_
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//
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// 8254 Timer
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//
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#define TIMER0_COUNT_PORT 0x40
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#define TIMER1_COUNT_PORT 0x41
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#define TIMER2_COUNT_PORT 0x42
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#define TIMER_CONTROL_PORT 0x43
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//
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// 8259 PIC interrupt controller
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//
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#define PIC_CONTROL_REGISTER_MASTER 0x20
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#define PIC_MASK_REGISTER_MASTER 0x21
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#define PIC_CONTROL_REGISTER_SLAVE 0xA0
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#define PIC_MASK_REGISTER_SLAVE 0xA1
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#define PIC_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER 0x4D0
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#define PIC_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE 0x4D1
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#define PIC_EOI 0x20
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//
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// 8237 DMA registers
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//
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#define R_8237_DMA_BASE_CA_CH0 0x00
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#define R_8237_DMA_BASE_CA_CH1 0x02
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#define R_8237_DMA_BASE_CA_CH2 0x04
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#define R_8237_DMA_BASE_CA_CH3 0xd6
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#define R_8237_DMA_BASE_CA_CH5 0xc4
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#define R_8237_DMA_BASE_CA_CH6 0xc8
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#define R_8237_DMA_BASE_CA_CH7 0xcc
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#define R_8237_DMA_BASE_CC_CH0 0x01
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#define R_8237_DMA_BASE_CC_CH1 0x03
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#define R_8237_DMA_BASE_CC_CH2 0x05
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#define R_8237_DMA_BASE_CC_CH3 0xd7
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#define R_8237_DMA_BASE_CC_CH5 0xc6
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#define R_8237_DMA_BASE_CC_CH6 0xca
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#define R_8237_DMA_BASE_CC_CH7 0xce
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#define R_8237_DMA_MEM_LP_CH0 0x87
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#define R_8237_DMA_MEM_LP_CH1 0x83
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#define R_8237_DMA_MEM_LP_CH2 0x81
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#define R_8237_DMA_MEM_LP_CH3 0x82
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#define R_8237_DMA_MEM_LP_CH5 0x8B
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#define R_8237_DMA_MEM_LP_CH6 0x89
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#define R_8237_DMA_MEM_LP_CH7 0x8A
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#define R_8237_DMA_COMMAND_CH0_3 0x08
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#define R_8237_DMA_COMMAND_CH4_7 0xd0
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#define B_8237_DMA_COMMAND_GAP 0x10
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#define B_8237_DMA_COMMAND_CGE 0x04
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#define R_8237_DMA_STA_CH0_3 0xd8
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#define R_8237_DMA_STA_CH4_7 0xd0
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#define R_8237_DMA_WRSMSK_CH0_3 0x0a
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#define R_8237_DMA_WRSMSK_CH4_7 0xd4
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#define B_8237_DMA_WRSMSK_CMS 0x04
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#define R_8237_DMA_CHMODE_CH0_3 0x0b
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#define R_8237_DMA_CHMODE_CH4_7 0xd6
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#define V_8237_DMA_CHMODE_DEMAND 0x00
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#define V_8237_DMA_CHMODE_SINGLE 0x40
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#define V_8237_DMA_CHMODE_CASCADE 0xc0
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#define B_8237_DMA_CHMODE_DECREMENT 0x20
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#define B_8237_DMA_CHMODE_INCREMENT 0x00
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#define B_8237_DMA_CHMODE_AE 0x10
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#define V_8237_DMA_CHMODE_VERIFY 0
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#define V_8237_DMA_CHMODE_IO2MEM 0x04
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#define V_8237_DMA_CHMODE_MEM2IO 0x08
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#define R_8237_DMA_CBPR_CH0_3 0x0c
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#define R_8237_DMA_CBPR_CH4_7 0xd8
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#define R_8237_DMA_MCR_CH0_3 0x0d
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#define R_8237_DMA_MCR_CH4_7 0xda
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#define R_8237_DMA_CLMSK_CH0_3 0x0e
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#define R_8237_DMA_CLMSK_CH4_7 0xdc
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#define R_8237_DMA_WRMSK_CH0_3 0x0f
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#define R_8237_DMA_WRMSK_CH4_7 0xde
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#endif
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