mirror of https://github.com/acidanthera/audk.git
135 lines
4.7 KiB
C
135 lines
4.7 KiB
C
/** @file
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Chipset/ARM926EJ-S.h>
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#include <Library/ArmLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/DebugLib.h>
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VOID
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FillTranslationTable (
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IN UINT32 *TranslationTable,
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IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
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)
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{
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UINT32 *Entry;
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UINTN Sections;
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UINTN Index;
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UINT32 Attributes;
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UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
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switch (MemoryRegion->Attributes) {
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case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
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Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
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Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH;
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
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Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED;
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break;
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case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
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case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
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case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
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ASSERT(0); // Trustzone is not supported on ARMv5
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default:
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Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED;
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break;
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}
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Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
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Sections = MemoryRegion->Length / TT_DESCRIPTOR_SECTION_SIZE;
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// The current code does not support memory region size that is not aligned on TT_DESCRIPTOR_SECTION_SIZE boundary
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ASSERT (MemoryRegion->Length % TT_DESCRIPTOR_SECTION_SIZE == 0);
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for (Index = 0; Index < Sections; Index++)
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{
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*Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
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PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
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}
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}
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RETURN_STATUS
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EFIAPI
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ArmConfigureMmu (
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IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
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OUT VOID **TranslationTableBase OPTIONAL,
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OUT UINTN *TranslationTableSize OPTIONAL
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)
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{
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VOID *TranslationTable;
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// Allocate pages for translation table.
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TranslationTable = AllocatePages (EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
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if (TranslationTable == NULL) {
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return RETURN_OUT_OF_RESOURCES;
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}
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TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
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if (TranslationTableBase != NULL) {
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*TranslationTableBase = TranslationTable;
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}
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if (TranslationTableBase != NULL) {
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*TranslationTableSize = TRANSLATION_TABLE_SIZE;
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}
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ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
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ArmCleanInvalidateDataCache();
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ArmInvalidateInstructionCache();
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ArmInvalidateTlb();
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ArmDisableDataCache();
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ArmDisableInstructionCache();
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ArmDisableMmu();
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// Make sure nothing sneaked into the cache
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ArmCleanInvalidateDataCache();
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ArmInvalidateInstructionCache();
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while (MemoryTable->Length != 0) {
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FillTranslationTable(TranslationTable, MemoryTable);
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MemoryTable++;
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}
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ArmSetTTBR0(TranslationTable);
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ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
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DOMAIN_ACCESS_CONTROL_NONE(14) |
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DOMAIN_ACCESS_CONTROL_NONE(13) |
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DOMAIN_ACCESS_CONTROL_NONE(12) |
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DOMAIN_ACCESS_CONTROL_NONE(11) |
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DOMAIN_ACCESS_CONTROL_NONE(10) |
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DOMAIN_ACCESS_CONTROL_NONE( 9) |
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DOMAIN_ACCESS_CONTROL_NONE( 8) |
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DOMAIN_ACCESS_CONTROL_NONE( 7) |
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DOMAIN_ACCESS_CONTROL_NONE( 6) |
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DOMAIN_ACCESS_CONTROL_NONE( 5) |
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DOMAIN_ACCESS_CONTROL_NONE( 4) |
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DOMAIN_ACCESS_CONTROL_NONE( 3) |
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DOMAIN_ACCESS_CONTROL_NONE( 2) |
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DOMAIN_ACCESS_CONTROL_NONE( 1) |
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DOMAIN_ACCESS_CONTROL_MANAGER(0));
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ArmEnableInstructionCache();
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ArmEnableDataCache();
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ArmEnableMmu();
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return RETURN_SUCCESS;
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}
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