mirror of https://github.com/acidanthera/audk.git
b97af6d42b
According to the ICH9 spec, PMBASE "provides 128 bytes of I/O space for ACPI, GPIO, and TCO logic. This is placed on a 128-byte boundary". On the Q35 machine type of QEMU, our current PMBASE setting of 0xB000 is the only thing that prevents us from lowering the base of the PCI IO port aperture from 0xC000. (The base must be aligned to 0x1000 due to PCI bridge requirements.) By moving our PMBASE to 0x0600 (moving the register block to 0x0600..0x067F inclusive), which is also what SeaBIOS uses on Q35, we will be able to lower the PCI IO port aperture base to 0x6000 (the next IO port under it being taken by the "vmport" device, at fixed 0x5658), while steering clear of other QEMU devices. On PIIX4, freeing up the 0x1000 IO ports at 0xB000 wouldn't help much, because the 0xA000 block right below it is occupied by unmovable devices (see <https://bugzilla.redhat.com/show_bug.cgi?id=1333238#c19> for details). Doing this for Q35 only has two more benefits: - It won't interfere with Xen guests, - The Q35 machine type with the smallest version number is "pc-q35-2.4", which is guaranteed to have an ACPI generator. This matters because the ACPI tables (FACP, DSDT) have to reflect the PM base address that we program. Cc: Gabriel Somlo <somlo@cmu.edu> Cc: Jordan Justen <jordan.l.justen@intel.com> Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1333238 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Tested-by: Gabriel Somlo <somlo@cmu.edu> |
||
|---|---|---|
| .. | ||
| Guid | ||
| IndustryStandard | ||
| Library | ||
| Protocol | ||
| Register | ||
| OvmfPlatforms.h | ||