mirror of
https://github.com/acidanthera/audk.git
synced 2025-07-17 10:44:24 +02:00
4059386c70
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
126 lines
2.5 KiB
C
126 lines
2.5 KiB
C
/** @file
|
|
|
|
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
|
Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
|
|
|
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
|
|
|
**/
|
|
#include <Base.h>
|
|
#include <Library/ArmLib.h>
|
|
#include <Library/DebugLib.h>
|
|
#include <Library/PcdLib.h>
|
|
|
|
STATIC
|
|
VOID
|
|
CacheRangeOperation (
|
|
IN VOID *Start,
|
|
IN UINTN Length,
|
|
IN LINE_OPERATION LineOperation,
|
|
IN UINTN LineLength
|
|
)
|
|
{
|
|
UINTN ArmCacheLineAlignmentMask = LineLength - 1;
|
|
|
|
// Align address (rounding down)
|
|
UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
|
|
UINTN EndAddress = (UINTN)Start + Length;
|
|
|
|
// Perform the line operation on an address in each cache line
|
|
while (AlignedAddress < EndAddress) {
|
|
LineOperation(AlignedAddress);
|
|
AlignedAddress += LineLength;
|
|
}
|
|
ArmDataSynchronizationBarrier ();
|
|
}
|
|
|
|
VOID
|
|
EFIAPI
|
|
InvalidateInstructionCache (
|
|
VOID
|
|
)
|
|
{
|
|
ASSERT (FALSE);
|
|
}
|
|
|
|
VOID
|
|
EFIAPI
|
|
InvalidateDataCache (
|
|
VOID
|
|
)
|
|
{
|
|
ASSERT (FALSE);
|
|
}
|
|
|
|
VOID *
|
|
EFIAPI
|
|
InvalidateInstructionCacheRange (
|
|
IN VOID *Address,
|
|
IN UINTN Length
|
|
)
|
|
{
|
|
CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryToPoUByMVA,
|
|
ArmDataCacheLineLength ());
|
|
CacheRangeOperation (Address, Length,
|
|
ArmInvalidateInstructionCacheEntryToPoUByMVA,
|
|
ArmInstructionCacheLineLength ());
|
|
|
|
ArmInstructionSynchronizationBarrier ();
|
|
|
|
return Address;
|
|
}
|
|
|
|
VOID
|
|
EFIAPI
|
|
WriteBackInvalidateDataCache (
|
|
VOID
|
|
)
|
|
{
|
|
ASSERT (FALSE);
|
|
}
|
|
|
|
VOID *
|
|
EFIAPI
|
|
WriteBackInvalidateDataCacheRange (
|
|
IN VOID *Address,
|
|
IN UINTN Length
|
|
)
|
|
{
|
|
CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCacheEntryByMVA,
|
|
ArmDataCacheLineLength ());
|
|
return Address;
|
|
}
|
|
|
|
VOID
|
|
EFIAPI
|
|
WriteBackDataCache (
|
|
VOID
|
|
)
|
|
{
|
|
ASSERT (FALSE);
|
|
}
|
|
|
|
VOID *
|
|
EFIAPI
|
|
WriteBackDataCacheRange (
|
|
IN VOID *Address,
|
|
IN UINTN Length
|
|
)
|
|
{
|
|
CacheRangeOperation(Address, Length, ArmCleanDataCacheEntryByMVA,
|
|
ArmDataCacheLineLength ());
|
|
return Address;
|
|
}
|
|
|
|
VOID *
|
|
EFIAPI
|
|
InvalidateDataCacheRange (
|
|
IN VOID *Address,
|
|
IN UINTN Length
|
|
)
|
|
{
|
|
CacheRangeOperation(Address, Length, ArmInvalidateDataCacheEntryByMVA,
|
|
ArmDataCacheLineLength ());
|
|
return Address;
|
|
}
|