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4059386c70
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
94 lines
2.9 KiB
NASM
94 lines
2.9 KiB
NASM
//------------------------------------------------------------------------------
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//
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// Copyright (c) 2011, ARM Limited. All rights reserved.
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//
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// SPDX-License-Identifier: BSD-2-Clause-Patent
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//
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//------------------------------------------------------------------------------
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INCLUDE AsmMacroExport.inc
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PRESERVE8
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RVCT_ASM_EXPORT ArmReadCntFrq
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mrc p15, 0, r0, c14, c0, 0 ; Read CNTFRQ
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bx lr
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RVCT_ASM_EXPORT ArmWriteCntFrq
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mcr p15, 0, r0, c14, c0, 0 ; Write to CNTFRQ
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bx lr
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RVCT_ASM_EXPORT ArmReadCntPct
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mrrc p15, 0, r0, r1, c14 ; Read CNTPT (Physical counter register)
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bx lr
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RVCT_ASM_EXPORT ArmReadCntkCtl
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mrc p15, 0, r0, c14, c1, 0 ; Read CNTK_CTL (Timer PL1 Control Register)
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bx lr
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RVCT_ASM_EXPORT ArmWriteCntkCtl
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mcr p15, 0, r0, c14, c1, 0 ; Write to CNTK_CTL (Timer PL1 Control Register)
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bx lr
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RVCT_ASM_EXPORT ArmReadCntpTval
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mrc p15, 0, r0, c14, c2, 0 ; Read CNTP_TVAL (PL1 physical timer value register)
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bx lr
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RVCT_ASM_EXPORT ArmWriteCntpTval
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mcr p15, 0, r0, c14, c2, 0 ; Write to CNTP_TVAL (PL1 physical timer value register)
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bx lr
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RVCT_ASM_EXPORT ArmReadCntpCtl
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mrc p15, 0, r0, c14, c2, 1 ; Read CNTP_CTL (PL1 Physical Timer Control Register)
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bx lr
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RVCT_ASM_EXPORT ArmWriteCntpCtl
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mcr p15, 0, r0, c14, c2, 1 ; Write to CNTP_CTL (PL1 Physical Timer Control Register)
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bx lr
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RVCT_ASM_EXPORT ArmReadCntvTval
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mrc p15, 0, r0, c14, c3, 0 ; Read CNTV_TVAL (Virtual Timer Value register)
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bx lr
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RVCT_ASM_EXPORT ArmWriteCntvTval
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mcr p15, 0, r0, c14, c3, 0 ; Write to CNTV_TVAL (Virtual Timer Value register)
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bx lr
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RVCT_ASM_EXPORT ArmReadCntvCtl
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mrc p15, 0, r0, c14, c3, 1 ; Read CNTV_CTL (Virtual Timer Control Register)
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bx lr
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RVCT_ASM_EXPORT ArmWriteCntvCtl
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mcr p15, 0, r0, c14, c3, 1 ; Write to CNTV_CTL (Virtual Timer Control Register)
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bx lr
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RVCT_ASM_EXPORT ArmReadCntvCt
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mrrc p15, 1, r0, r1, c14 ; Read CNTVCT (Virtual Count Register)
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bx lr
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RVCT_ASM_EXPORT ArmReadCntpCval
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mrrc p15, 2, r0, r1, c14 ; Read CNTP_CTVAL (Physical Timer Compare Value Register)
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bx lr
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RVCT_ASM_EXPORT ArmWriteCntpCval
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mcrr p15, 2, r0, r1, c14 ; Write to CNTP_CTVAL (Physical Timer Compare Value Register)
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bx lr
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RVCT_ASM_EXPORT ArmReadCntvCval
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mrrc p15, 3, r0, r1, c14 ; Read CNTV_CTVAL (Virtual Timer Compare Value Register)
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bx lr
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RVCT_ASM_EXPORT ArmWriteCntvCval
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mcrr p15, 3, r0, r1, c14 ; write to CNTV_CTVAL (Virtual Timer Compare Value Register)
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bx lr
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RVCT_ASM_EXPORT ArmReadCntvOff
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mrrc p15, 4, r0, r1, c14 ; Read CNTVOFF (virtual Offset register)
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bx lr
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RVCT_ASM_EXPORT ArmWriteCntvOff
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mcrr p15, 4, r0, r1, c14 ; Write to CNTVOFF (Virtual Offset register)
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bx lr
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END
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