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9344f09215
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
84 lines
2.6 KiB
C
84 lines
2.6 KiB
C
/** @file
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IA-32/x64 PatchInstructionX86()
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Copyright (C) 2018, Intel Corporation. All rights reserved.<BR>
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Copyright (C) 2018, Red Hat, Inc.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "BaseLibInternals.h"
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/**
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Patch the immediate operand of an IA32 or X64 instruction such that the byte,
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word, dword or qword operand is encoded at the end of the instruction's
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binary representation.
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This function should be used to update object code that was compiled with
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NASM from assembly source code. Example:
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NASM source code:
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mov eax, strict dword 0 ; the imm32 zero operand will be patched
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ASM_PFX(gPatchCr3):
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mov cr3, eax
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C source code:
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X86_ASSEMBLY_PATCH_LABEL gPatchCr3;
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PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4);
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@param[out] InstructionEnd Pointer right past the instruction to patch. The
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immediate operand to patch is expected to
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comprise the trailing bytes of the instruction.
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If InstructionEnd is closer to address 0 than
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ValueSize permits, then ASSERT().
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@param[in] PatchValue The constant to write to the immediate operand.
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The caller is responsible for ensuring that
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PatchValue can be represented in the byte, word,
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dword or qword operand (as indicated through
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ValueSize); otherwise ASSERT().
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@param[in] ValueSize The size of the operand in bytes; must be 1, 2,
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4, or 8. ASSERT() otherwise.
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**/
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VOID
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EFIAPI
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PatchInstructionX86 (
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OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,
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IN UINT64 PatchValue,
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IN UINTN ValueSize
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)
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{
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//
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// The equality ((UINTN)InstructionEnd == ValueSize) would assume a zero-size
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// instruction at address 0; forbid it.
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//
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ASSERT ((UINTN)InstructionEnd > ValueSize);
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switch (ValueSize) {
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case 1:
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ASSERT (PatchValue <= MAX_UINT8);
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*((UINT8 *)(UINTN)InstructionEnd - 1) = (UINT8)PatchValue;
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break;
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case 2:
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ASSERT (PatchValue <= MAX_UINT16);
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WriteUnaligned16 ((UINT16 *)(UINTN)InstructionEnd - 1, (UINT16)PatchValue);
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break;
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case 4:
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ASSERT (PatchValue <= MAX_UINT32);
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WriteUnaligned32 ((UINT32 *)(UINTN)InstructionEnd - 1, (UINT32)PatchValue);
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break;
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case 8:
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WriteUnaligned64 ((UINT64 *)(UINTN)InstructionEnd - 1, PatchValue);
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break;
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default:
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ASSERT (FALSE);
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}
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}
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