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0acd869796
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
69 lines
1.7 KiB
NASM
69 lines
1.7 KiB
NASM
;------------------------------------------------------------------------------
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;*
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;* Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
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;* SPDX-License-Identifier: BSD-2-Clause-Patent
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;*
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;*
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;------------------------------------------------------------------------------
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SECTION .rodata
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;
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; Float control word initial value:
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; all exceptions masked, double-precision, round-to-nearest
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;
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mFpuControlWord: DW 0x27F
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;
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; Multimedia-extensions control word:
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; all exceptions masked, round-to-nearest, flush to zero for masked underflow
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;
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mMmxControlWord: DD 0x1F80
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SECTION .text
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;
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; Initializes floating point units for requirement of UEFI specification.
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;
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; This function initializes floating-point control word to 0x027F (all exceptions
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; masked,double-precision, round-to-nearest) and multimedia-extensions control word
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; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
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; for masked underflow).
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;
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global ASM_PFX(InitializeFloatingPointUnits)
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ASM_PFX(InitializeFloatingPointUnits):
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push ebx
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;
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; Initialize floating point units
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;
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finit
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fldcw [mFpuControlWord]
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;
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; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
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; whether the processor supports SSE instruction.
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;
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mov eax, 1
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cpuid
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bt edx, 25
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jnc Done
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;
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; Set OSFXSR bit 9 in CR4
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;
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mov eax, cr4
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or eax, BIT9
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mov cr4, eax
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;
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; The processor should support SSE instruction and we can use
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; ldmxcsr instruction
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;
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ldmxcsr [mMmxControlWord]
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Done:
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pop ebx
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ret
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