mirror of https://github.com/acidanthera/audk.git
141 lines
4.2 KiB
PHP
141 lines
4.2 KiB
PHP
;
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; Copyright (c) 2013-2015 Intel Corporation.
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;
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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;------------------------------------------------------------------------------
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;
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; Module Name:
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;
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; Platform.inc
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;
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; Abstract:
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;
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; Quark A0 Platform Specific Definitions
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;
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;------------------------------------------------------------------------------
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JMP32 MACRO FunctionName
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lea esp, @F
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jmp FunctionName
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@@:
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ENDM
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RET32 MACRO
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jmp esp
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ENDM
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;
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; ROM/SPI/MEMORY Definitions
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;
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QUARK_DDR3_MEM_BASE_ADDRESS EQU 000000000h ; Memory Base Address = 0
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QUARK_MAX_DDR3_MEM_SIZE_BYTES EQU 080000000h ; DDR3 Memory Size = 2GB
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QUARK_ESRAM_MEM_SIZE_BYTES EQU 000080000h ; eSRAM Memory Size = 512K
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QUARK_STACK_SIZE_BYTES EQU 008000h ; Quark stack size = 32K
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;
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; RTC/CMOS definitions
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;
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RTC_INDEX EQU 070h
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NMI_DISABLE EQU 080h ; Bit7=1 disables NMI
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NMI_ENABLE EQU 000h ; Bit7=0 disables NMI
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RTC_DATA EQU 071h
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;
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; PCI Configuration definitions
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;
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PCI_CFG EQU 1 SHL 01Fh ; PCI configuration access mechanism
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PCI_ADDRESS_PORT EQU 0CF8h
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PCI_DATA_PORT EQU 0CFCh
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;
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; Quark PCI devices
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;
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HOST_BRIDGE_PFA EQU 0000h ; B0:D0:F0 (Host Bridge)
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ILB_PFA EQU 00F8h ; B0:D31:F0 (Legacy Block)
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;
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; ILB PCI Config Registers
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;
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BDE EQU 0D4h ; BIOS Decode Enable register
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DECODE_ALL_REGIONS_ENABLE EQU 0FF000000h ; Decode all BIOS decode ranges
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;
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; iLB Reset Register
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;
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ILB_RESET_REG EQU 0CF9h
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CF9_WARM_RESET EQU 02h
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CF9_COLD_RESET EQU 08h
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;
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; Host Bridge PCI Config Registers
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;
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MESSAGE_BUS_CONTROL_REG EQU 0D0h ; Message Bus Control Register
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SB_OPCODE_FIELD EQU 018h ; Bit location of Opcode field
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OPCODE_SIDEBAND_REG_READ EQU 010h ; Read opcode
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OPCODE_SIDEBAND_REG_WRITE EQU 011h ; Write opcode
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OPCODE_SIDEBAND_ALT_REG_READ EQU 06h ; Alternate Read opcode
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OPCODE_SIDEBAND_ALT_REG_WRITE EQU 07h ; Alternate Write opcode
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OPCODE_WARM_RESET_REQUEST EQU 0F4h ; Reset Warm
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OPCODE_COLD_RESET_REQUEST EQU 0F5h ; Reset Cold
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SB_PORT_FIELD EQU 010h ; Bit location of Port ID field
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MEMORY_ARBITER_PORT_ID EQU 00h
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HOST_BRIDGE_PORT_ID EQU 03h
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RMU_PORT_ID EQU 04h
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MEMORY_MANAGER_PORT_ID EQU 05h
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SOC_UNIT_PORT_ID EQU 031h
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SB_ADDR_FIELD EQU 008h ; Bit location of Register field
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SB_BE_FIELD EQU 004h ; Bit location of Byte Enables field
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ALL_BYTE_EN EQU 00Fh ; All Byte Enables
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MESSAGE_DATA_REG EQU 0D4h ; Message Data Register
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;
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; Memory Arbiter Config Registers
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;
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AEC_CTRL_OFFSET EQU 00h
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;
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; Host Bridge Config Registers
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;
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HMISC2_OFFSET EQU 03h
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OR_PM_FIELD EQU 010h
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SMI_EN EQU 1 SHL 13h
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HMBOUND_OFFSET EQU 08h
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HMBOUND_ADDRESS EQU (QUARK_DDR3_MEM_BASE_ADDRESS + QUARK_MAX_DDR3_MEM_SIZE_BYTES + QUARK_ESRAM_MEM_SIZE_BYTES)
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HMBOUND_LOCK EQU 00000001h
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HECREG_OFFSET EQU 09h
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EC_BASE EQU 0E0000000h
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EC_ENABLE EQU 01h
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HLEGACY_OFFSET EQU 0Ah
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NMI EQU 1 SHL 0Eh ; Pin 14
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SMI EQU 1 SHL 0Ch ; Pin 12
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INTR EQU 1 SHL 0Ah ; Pin 10
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;
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; Memory Manager Config Registers
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;
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ESRAMPGCTRL_BLOCK_OFFSET EQU 082h
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BLOCK_ENABLE_PG EQU 010000000h
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BIMRVCTL_OFFSET EQU 019h
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ENABLE_IMR_INTERRUPT EQU 080000000h
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;
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; SOC UNIT Debug Registers
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;
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CFGSTICKY_W1_OFFSET EQU 050h
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FORCE_COLD_RESET EQU 00000001h
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CFGSTICKY_RW_OFFSET EQU 051h
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RESET_FOR_ESRAM_LOCK EQU 00000020h
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RESET_FOR_HMBOUND_LOCK EQU 00000040h
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CFGNONSTICKY_W1_OFFSET EQU 052h
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FORCE_WARM_RESET EQU 00000001h
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