mirror of https://github.com/acidanthera/audk.git
ded0b489af
Implement the SpeculationBarrier with implementations consisting of fence instruction which provides finer-grain memory orderings. Perform Data Barrier in RiscV: fence rw,rw Perform Instruction Barrier in RiscV: fence.i; fence r,r More detail is in Appendix A: RVWMO Explanatory Material in https://github.com/riscv/riscv-isa-manual This API is first introduced in the below commits for IA32 and x64 |
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Include | ||
Library | ||
Test | ||
MdeLibs.dsc.inc | ||
MdePkg.ci.yaml | ||
MdePkg.dec | ||
MdePkg.dsc | ||
MdePkg.uni | ||
MdePkgExtra.uni |