mirror of https://github.com/acidanthera/audk.git
114 lines
2.7 KiB
ArmAsm
114 lines
2.7 KiB
ArmAsm
#------------------------------------------------------------------------------
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#
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# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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#include <AsmMacroIoLib.h>
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.text
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.align 2
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GCC_ASM_EXPORT(ArmIsMpCore)
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GCC_ASM_EXPORT(ArmEnableAsynchronousAbort)
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GCC_ASM_EXPORT(ArmDisableAsynchronousAbort)
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GCC_ASM_EXPORT(ArmEnableIrq)
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GCC_ASM_EXPORT(ArmDisableIrq)
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GCC_ASM_EXPORT(ArmEnableFiq)
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GCC_ASM_EXPORT(ArmDisableFiq)
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GCC_ASM_EXPORT(ArmEnableInterrupts)
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GCC_ASM_EXPORT(ArmDisableInterrupts)
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GCC_ASM_EXPORT(ReadCCSIDR)
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GCC_ASM_EXPORT(ReadCLIDR)
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GCC_ASM_EXPORT(ArmReadNsacr)
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GCC_ASM_EXPORT(ArmWriteNsacr)
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#------------------------------------------------------------------------------
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ASM_PFX(ArmIsMpCore):
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mrc p15,0,R0,c0,c0,5
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// Get Multiprocessing extension (bit31) & U bit (bit30)
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and R0, R0, #0xC0000000
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// if (bit31 == 1) && (bit30 == 0) then the processor is part of a multiprocessor system
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cmp R0, #0x80000000
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moveq R0, #1
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movne R0, #0
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bx LR
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ASM_PFX(ArmEnableAsynchronousAbort):
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cpsie a
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isb
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bx LR
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ASM_PFX(ArmDisableAsynchronousAbort):
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cpsid a
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isb
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bx LR
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ASM_PFX(ArmEnableIrq):
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cpsie i
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isb
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bx LR
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ASM_PFX(ArmDisableIrq):
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cpsid i
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isb
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bx LR
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ASM_PFX(ArmEnableFiq):
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cpsie f
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isb
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bx LR
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ASM_PFX(ArmDisableFiq):
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cpsid f
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isb
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bx LR
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ASM_PFX(ArmEnableInterrupts):
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cpsie if
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isb
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bx LR
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ASM_PFX(ArmDisableInterrupts):
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cpsid if
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isb
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bx LR
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// UINT32
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// ReadCCSIDR (
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// IN UINT32 CSSELR
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// )
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ASM_PFX(ReadCCSIDR):
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mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)
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isb
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mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)
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bx lr
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// UINT32
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// ReadCLIDR (
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// IN UINT32 CSSELR
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// )
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ASM_PFX(ReadCLIDR):
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mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register
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bx lr
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ASM_PFX(ArmReadNsacr):
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mrc p15, 0, r0, c1, c1, 2
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bx lr
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ASM_PFX(ArmWriteNsacr):
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mcr p15, 0, r0, c1, c1, 2
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bx lr
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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