mirror of https://github.com/acidanthera/audk.git
464 lines
11 KiB
C
464 lines
11 KiB
C
/**@file
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Platform PEI driver
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Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
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Copyright (c) 2019, Citrix Systems, Inc.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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//
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// The package level header files this module uses
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//
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#include <PiPei.h>
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//
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// The Library classes this module consumes
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//
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#include <Library/BaseLib.h>
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#include <Library/DebugLib.h>
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#include <Library/HobLib.h>
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#include <Library/IoLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PciLib.h>
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#include <Library/PeimEntryPoint.h>
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#include <Library/PeiServicesLib.h>
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#include <Library/ResourcePublicationLib.h>
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#include <Guid/MemoryTypeInformation.h>
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#include <Ppi/MasterBootMode.h>
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#include <IndustryStandard/Pci22.h>
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#include <OvmfPlatforms.h>
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#include "Platform.h"
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#include "Cmos.h"
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EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
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{ EfiACPIMemoryNVS, 0x004 },
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{ EfiACPIReclaimMemory, 0x008 },
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{ EfiReservedMemoryType, 0x004 },
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{ EfiRuntimeServicesData, 0x024 },
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{ EfiRuntimeServicesCode, 0x030 },
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{ EfiBootServicesCode, 0x180 },
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{ EfiBootServicesData, 0xF00 },
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{ EfiMaxMemoryType, 0x000 }
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};
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EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {
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{
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EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
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&gEfiPeiMasterBootModePpiGuid,
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NULL
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}
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};
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UINT16 mHostBridgeDevId;
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EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
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VOID
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AddIoMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize
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)
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{
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BuildResourceDescriptorHob (
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EFI_RESOURCE_MEMORY_MAPPED_IO,
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_TESTED,
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MemoryBase,
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MemorySize
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);
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}
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VOID
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AddReservedMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize,
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BOOLEAN Cacheable
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)
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{
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BuildResourceDescriptorHob (
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EFI_RESOURCE_MEMORY_RESERVED,
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
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(Cacheable ?
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EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
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0
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) |
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EFI_RESOURCE_ATTRIBUTE_TESTED,
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MemoryBase,
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MemorySize
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);
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}
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VOID
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AddReservedMemoryRangeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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EFI_PHYSICAL_ADDRESS MemoryLimit,
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BOOLEAN Cacheable
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)
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{
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AddReservedMemoryBaseSizeHob (MemoryBase,
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(UINT64)(MemoryLimit - MemoryBase), Cacheable);
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}
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VOID
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AddIoMemoryRangeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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EFI_PHYSICAL_ADDRESS MemoryLimit
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)
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{
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AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
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}
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VOID
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AddMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize
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)
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{
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BuildResourceDescriptorHob (
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EFI_RESOURCE_SYSTEM_MEMORY,
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_TESTED,
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MemoryBase,
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MemorySize
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);
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}
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VOID
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AddMemoryRangeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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EFI_PHYSICAL_ADDRESS MemoryLimit
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)
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{
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AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
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}
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VOID
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MemMapInitialization (
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VOID
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)
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{
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UINT64 PciIoBase;
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UINT64 PciIoSize;
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RETURN_STATUS PcdStatus;
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PciIoBase = 0xC000;
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PciIoSize = 0x4000;
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//
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// Create Memory Type Information HOB
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//
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BuildGuidDataHob (
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&gEfiMemoryTypeInformationGuid,
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mDefaultMemoryTypeInformation,
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sizeof(mDefaultMemoryTypeInformation)
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);
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//
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// Video memory + Legacy BIOS region
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//
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AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
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//
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// Add PCI IO Port space available for PCI resource allocations.
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//
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BuildResourceDescriptorHob (
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EFI_RESOURCE_IO,
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
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PciIoBase,
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PciIoSize
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);
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PcdStatus = PcdSet64S (PcdPciIoBase, PciIoBase);
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ASSERT_RETURN_ERROR (PcdStatus);
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PcdStatus = PcdSet64S (PcdPciIoSize, PciIoSize);
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ASSERT_RETURN_ERROR (PcdStatus);
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}
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VOID
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PciExBarInitialization (
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VOID
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)
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{
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union {
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UINT64 Uint64;
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UINT32 Uint32[2];
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} PciExBarBase;
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//
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// We only support the 256MB size for the MMCONFIG area:
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// 256 buses * 32 devices * 8 functions * 4096 bytes config space.
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//
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// The masks used below enforce the Q35 requirements that the MMCONFIG area
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// be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.
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//
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// Note that (b) also ensures that the minimum address width we have
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// determined in AddressWidthInitialization(), i.e., 36 bits, will suffice
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// for DXE's page tables to cover the MMCONFIG area.
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//
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PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);
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ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);
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ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);
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//
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// Clear the PCIEXBAREN bit first, before programming the high register.
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//
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PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);
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//
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// Program the high register. Then program the low register, setting the
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// MMCONFIG area size and enabling decoding at once.
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//
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PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);
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PciWrite32 (
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DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),
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PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN
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);
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}
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VOID
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MiscInitialization (
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VOID
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)
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{
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UINTN PmCmd;
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UINTN Pmba;
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UINT32 PmbaAndVal;
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UINT32 PmbaOrVal;
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UINTN AcpiCtlReg;
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UINT8 AcpiEnBit;
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RETURN_STATUS PcdStatus;
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//
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// Disable A20 Mask
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//
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IoOr8 (0x92, BIT1);
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//
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// Build the CPU HOB with guest RAM size dependent address width and 16-bits
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// of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
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// S3 resume as well, so we build it unconditionally.)
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//
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BuildCpuHob (mPhysMemAddressWidth, 16);
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//
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// Determine platform type and save Host Bridge DID to PCD
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//
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switch (mHostBridgeDevId) {
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case INTEL_82441_DEVICE_ID:
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PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
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Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
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PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;
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PmbaOrVal = PIIX4_PMBA_VALUE;
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AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
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AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;
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break;
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case INTEL_Q35_MCH_DEVICE_ID:
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PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
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Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
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PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;
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PmbaOrVal = ICH9_PMBASE_VALUE;
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AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
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AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;
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break;
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default:
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if (XenPvhDetected ()) {
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//
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// There is no PCI bus in this case
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//
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return;
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}
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DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
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__FUNCTION__, mHostBridgeDevId));
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ASSERT (FALSE);
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return;
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}
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PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
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ASSERT_RETURN_ERROR (PcdStatus);
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//
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// If the appropriate IOspace enable bit is set, assume the ACPI PMBA
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// has been configured (e.g., by Xen) and skip the setup here.
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// This matches the logic in AcpiTimerLibConstructor ().
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//
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if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
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//
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// The PEI phase should be exited with fully accessibe ACPI PM IO space:
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// 1. set PMBA
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//
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PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);
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//
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// 2. set PCICMD/IOSE
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//
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PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
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//
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// 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
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//
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PciOr8 (AcpiCtlReg, AcpiEnBit);
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}
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if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
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//
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// Set Root Complex Register Block BAR
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//
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PciWrite32 (
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POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),
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ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN
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);
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//
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// Set PCI Express Register Range Base Address
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//
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PciExBarInitialization ();
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}
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}
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VOID
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BootModeInitialization (
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VOID
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)
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{
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EFI_STATUS Status;
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if (CmosRead8 (0xF) == 0xFE) {
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mBootMode = BOOT_ON_S3_RESUME;
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}
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CmosWrite8 (0xF, 0x00);
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Status = PeiServicesSetBootMode (mBootMode);
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ASSERT_EFI_ERROR (Status);
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Status = PeiServicesInstallPpi (mPpiBootMode);
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ASSERT_EFI_ERROR (Status);
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}
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VOID
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ReserveEmuVariableNvStore (
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)
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{
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EFI_PHYSICAL_ADDRESS VariableStore;
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RETURN_STATUS PcdStatus;
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//
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// Allocate storage for NV variables early on so it will be
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// at a consistent address. Since VM memory is preserved
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// across reboots, this allows the NV variable storage to survive
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// a VM reboot.
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//
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VariableStore =
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(EFI_PHYSICAL_ADDRESS)(UINTN)
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AllocateRuntimePages (
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EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))
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);
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DEBUG ((DEBUG_INFO,
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"Reserved variable store memory: 0x%lX; size: %dkb\n",
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VariableStore,
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(2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
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));
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PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);
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ASSERT_RETURN_ERROR (PcdStatus);
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}
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VOID
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DebugDumpCmos (
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VOID
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)
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{
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UINT32 Loop;
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DEBUG ((DEBUG_INFO, "CMOS:\n"));
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for (Loop = 0; Loop < 0x80; Loop++) {
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if ((Loop % 0x10) == 0) {
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DEBUG ((DEBUG_INFO, "%02x:", Loop));
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}
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DEBUG ((DEBUG_INFO, " %02x", CmosRead8 (Loop)));
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if ((Loop % 0x10) == 0xf) {
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DEBUG ((DEBUG_INFO, "\n"));
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}
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}
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}
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/**
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Perform Platform PEI initialization.
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@param FileHandle Handle of the file being invoked.
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@param PeiServices Describes the list of possible PEI Services.
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@return EFI_SUCCESS The PEIM initialized successfully.
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**/
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EFI_STATUS
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EFIAPI
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InitializeXenPlatform (
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IN EFI_PEI_FILE_HANDLE FileHandle,
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IN CONST EFI_PEI_SERVICES **PeiServices
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)
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{
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DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));
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DebugDumpCmos ();
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if (!XenDetect ()) {
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DEBUG ((DEBUG_ERROR, "ERROR: Xen isn't detected\n"));
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ASSERT (FALSE);
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CpuDeadLoop ();
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}
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XenConnect ();
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BootModeInitialization ();
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AddressWidthInitialization ();
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//
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// Query Host Bridge DID
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//
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mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
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PublishPeiMemory ();
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InitializeRamRegions ();
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InitializeXen ();
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if (mBootMode != BOOT_ON_S3_RESUME) {
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ReserveEmuVariableNvStore ();
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PeiFvInitialization ();
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MemMapInitialization ();
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}
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InstallClearCacheCallback ();
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AmdSevInitialize ();
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MiscInitialization ();
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return EFI_SUCCESS;
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}
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