mirror of https://github.com/acidanthera/audk.git
468 lines
24 KiB
Plaintext
468 lines
24 KiB
Plaintext
## @file UefiCpuPkg.dec
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# This Package provides UEFI compatible CPU modules and libraries.
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#
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# Copyright (c) 2007 - 2023, Intel Corporation. All rights reserved.<BR>
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# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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##
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[Defines]
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DEC_SPECIFICATION = 0x00010005
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PACKAGE_NAME = UefiCpuPkg
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PACKAGE_UNI_FILE = UefiCpuPkg.uni
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PACKAGE_GUID = 2171df9b-0d39-45aa-ac37-2de190010d23
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PACKAGE_VERSION = 0.90
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[Includes]
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Include
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[LibraryClasses]
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## @libraryclass Defines some routines that are used to register/manage/program
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## CPU features.
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##
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RegisterCpuFeaturesLib|Include/Library/RegisterCpuFeaturesLib.h
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[LibraryClasses.IA32, LibraryClasses.X64]
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## @libraryclass Provides functions to manage MTRR settings on IA32 and X64 CPUs.
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##
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MtrrLib|Include/Library/MtrrLib.h
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## @libraryclass Provides functions to manage the Local APIC on IA32 and X64 CPUs.
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##
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LocalApicLib|Include/Library/LocalApicLib.h
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## @libraryclass Provides platform specific initialization functions in the SEC phase.
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##
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PlatformSecLib|Include/Library/PlatformSecLib.h
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## @libraryclass Public include file for the SMM CPU Platform Hook Library.
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##
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SmmCpuPlatformHookLib|Include/Library/SmmCpuPlatformHookLib.h
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## @libraryclass Provides the CPU specific programming for PiSmmCpuDxeSmm module.
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##
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SmmCpuFeaturesLib|Include/Library/SmmCpuFeaturesLib.h
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## @libraryclass Provides functions to support MP services on CpuMpPei and CpuDxe module.
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##
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MpInitLib|Include/Library/MpInitLib.h
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## @libraryclass Provides function to support CcExit processing.
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CcExitLib|Include/Library/CcExitLib.h
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## @libraryclass Provides function to get CPU cache information.
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CpuCacheInfoLib|Include/Library/CpuCacheInfoLib.h
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## @libraryclass Provides function for loading microcode.
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MicrocodeLib|Include/Library/MicrocodeLib.h
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## @libraryclass Provides function for manipulating x86 paging structures.
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CpuPageTableLib|Include/Library/CpuPageTableLib.h
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## @libraryclass Provides functions for manipulating smram savestate registers.
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MmSaveStateLib|Include/Library/MmSaveStateLib.h
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[LibraryClasses.RISCV64]
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## @libraryclass Provides functions to manage MMU features on RISCV64 CPUs.
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##
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RiscVMmuLib|Include/Library/BaseRiscVMmuLib.h
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[Guids]
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gUefiCpuPkgTokenSpaceGuid = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}
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gMsegSmramGuid = { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }}
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## Include/Guid/CpuFeaturesSetDone.h
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gEdkiiCpuFeaturesSetDoneGuid = { 0xa82485ce, 0xad6b, 0x4101, { 0x99, 0xd3, 0xe1, 0x35, 0x8c, 0x9e, 0x7e, 0x37 }}
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## Include/Guid/CpuFeaturesInitDone.h
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gEdkiiCpuFeaturesInitDoneGuid = { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }}
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## Include/Guid/MicrocodePatchHob.h
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gEdkiiMicrocodePatchHobGuid = { 0xd178f11d, 0x8716, 0x418e, { 0xa1, 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }}
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## Include/Guid/SmmBaseHob.h
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gSmmBaseHobGuid = { 0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c, 0x25, 0xc5, 0xfc, 0x9d, 0x73 }}
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[Protocols]
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## Include/Protocol/SmmCpuService.h
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gEfiSmmCpuServiceProtocolGuid = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }}
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gEdkiiSmmCpuRendezvousProtocolGuid = { 0xaa00d50b, 0x4911, 0x428f, { 0xb9, 0x1a, 0xa5, 0x9d, 0xdb, 0x13, 0xe2, 0x4c }}
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## Include/Protocol/SmMonitorInit.h
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gEfiSmMonitorInitProtocolGuid = { 0x228f344d, 0xb3de, 0x43bb, { 0xa4, 0xd7, 0xea, 0x20, 0xb, 0x1b, 0x14, 0x82 }}
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[Protocols.RISCV64]
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#
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# Protocols defined for RISC-V systems
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#
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## Include/Protocol/RiscVBootProtocol.h
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gRiscVEfiBootProtocolGuid = { 0xccd15fec, 0x6f73, 0x4eec, { 0x83, 0x95, 0x3e, 0x69, 0xe4, 0xb9, 0x40, 0xbf }}
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#
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# [Error.gUefiCpuPkgTokenSpaceGuid]
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# 0x80000001 | Invalid value provided.
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#
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[Ppis]
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gEdkiiPeiMpServices2PpiGuid = { 0x5cb9cb3d, 0x31a4, 0x480c, { 0x94, 0x98, 0x29, 0xd2, 0x69, 0xba, 0xcf, 0xba}}
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## Include/Ppi/ShadowMicrocode.h
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gEdkiiPeiShadowMicrocodePpiGuid = { 0x430f6965, 0x9a69, 0x41c5, { 0x93, 0xed, 0x8b, 0xf0, 0x64, 0x35, 0xc1, 0xc6 }}
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## Include/Ppi/RepublishSecPpi.h
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gRepublishSecPpiPpiGuid = { 0x27a71b1e, 0x73ee, 0x43d6, { 0xac, 0xe3, 0x52, 0x1a, 0x2d, 0xc5, 0xd0, 0x92 }}
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[PcdsFeatureFlag]
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## Indicates if SMM Profile will be enabled.
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# If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged.
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# In X64 build, it could not be enabled when PcdCpuSmmRestrictedMemoryAccess is TRUE.
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# In IA32 build, the page table memory is not marked as read-only when it is enabled.
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# This PCD is only for validation purpose. It should be set to false in production.<BR><BR>
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# TRUE - SMM Profile will be enabled.<BR>
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# FALSE - SMM Profile will be disabled.<BR>
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# @Prompt Enable SMM Profile.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE|BOOLEAN|0x32132109
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## Indicates if the SMM profile log buffer is a ring buffer.
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# If disabled, no additional log can be done when the buffer is full.<BR><BR>
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# TRUE - the SMM profile log buffer is a ring buffer.<BR>
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# FALSE - the SMM profile log buffer is a normal buffer.<BR>
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# @Prompt The SMM profile log buffer is a ring buffer.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileRingBuffer|FALSE|BOOLEAN|0x3213210a
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## Indicates if SMM Startup AP in a blocking fashion.
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# TRUE - SMM Startup AP in a blocking fashion.<BR>
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# FALSE - SMM Startup AP in a non-blocking fashion.<BR>
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# @Prompt SMM Startup AP in a blocking fashion.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|FALSE|BOOLEAN|0x32132108
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## Indicates if SMM Stack Guard will be enabled.
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# If enabled, stack overflow in SMM can be caught, preventing chaotic consequences.<BR><BR>
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# TRUE - SMM Stack Guard will be enabled.<BR>
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# FALSE - SMM Stack Guard will be disabled.<BR>
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# @Prompt Enable SMM Stack Guard.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|TRUE|BOOLEAN|0x1000001C
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## Indicates if BSP election in SMM will be enabled.
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# If enabled, a BSP will be dynamically elected among all processors in each SMI.
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# Otherwise, processor 0 is always as BSP in each SMI.<BR><BR>
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# TRUE - BSP election in SMM will be enabled.<BR>
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# FALSE - BSP election in SMM will be disabled.<BR>
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# @Prompt Enable BSP election in SMM.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE|BOOLEAN|0x32132106
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## Indicates if CPU SMM hot-plug will be enabled.<BR><BR>
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# TRUE - SMM CPU hot-plug will be enabled.<BR>
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# FALSE - SMM CPU hot-plug will be disabled.<BR>
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# @Prompt SMM CPU hot-plug.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE|BOOLEAN|0x3213210C
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## Indicates if SMM Debug will be enabled.
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# If enabled, hardware breakpoints in SMRAM can be set outside of SMM mode and take effect in SMM.<BR><BR>
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# TRUE - SMM Debug will be enabled.<BR>
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# FALSE - SMM Debug will be disabled.<BR>
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# @Prompt Enable SMM Debug.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|FALSE|BOOLEAN|0x1000001B
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## Indicates if lock SMM Feature Control MSR.<BR><BR>
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# TRUE - SMM Feature Control MSR will be locked.<BR>
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# FALSE - SMM Feature Control MSR will not be locked.<BR>
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# @Prompt Lock SMM Feature Control MSR.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|TRUE|BOOLEAN|0x3213210B
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## Indicates if SMRR will be enabled.<BR><BR>
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# TRUE - SMRR will be enabled.<BR>
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# FALSE - SMRR will not be enabled.<BR>
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# @Prompt Enable SMRR.
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gUefiCpuPkgTokenSpaceGuid.PcdSmrrEnable|TRUE|BOOLEAN|0x3213210D
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## Indicates if SmmFeatureControl will be enabled.<BR><BR>
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# TRUE - SmmFeatureControl will be enabled.<BR>
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# FALSE - SmmFeatureControl will not be enabled.<BR>
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# @Prompt Support SmmFeatureControl.
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gUefiCpuPkgTokenSpaceGuid.PcdSmmFeatureControlEnable|TRUE|BOOLEAN|0x32132110
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## Indicates if SMM perf logging in APs will be enabled.<BR><BR>
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# TRUE - SMM perf logging in APs will be enabled.<BR>
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# FALSE - SMM perf logging in APs will not be enabled.<BR>
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# @Prompt Enable SMM perf logging in APs.
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gUefiCpuPkgTokenSpaceGuid.PcdSmmApPerfLogEnable|TRUE|BOOLEAN|0x32132114
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[PcdsFixedAtBuild]
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## List of exception vectors which need switching stack.
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# This PCD will only take into effect if PcdCpuStackGuard is enabled.
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# By default exception #DD(8), #PF(14) are supported.
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# @Prompt Specify exception vectors which need switching stack.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList|{0x08, 0x0E}|VOID*|0x30002000
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## Size of good stack for an exception.
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# This PCD will only take into effect if PcdCpuStackGuard is enabled.
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# @Prompt Specify size of good stack of exception which need switching stack.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize|2048|UINT32|0x30002001
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## Count of pre allocated SMM MP tokens per chunk.
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# @Prompt Specify the count of pre allocated SMM MP tokens per chunk.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmMpTokenCountPerChunk|64|UINT32|0x30002002
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## Area of memory where the SEV-ES work area block lives.
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# @Prompt Configure the SEV-ES work area base
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gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase|0x0|UINT32|0x30002005
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## Size of teh area of memory where the SEV-ES work area block lives.
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# @Prompt Configure the SEV-ES work area base
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gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaSize|0x0|UINT32|0x30002006
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## Determining APs' first-time wakeup by SIPI or INIT-SIPI-SIPI.
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# Following a power-up or RESET of an MP system, The APs complete a
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# minimal self-configuration, then wait for a startup signal (a SIPI
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# message) from the BSP processor.
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#
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# TRUE - Broadcast SIPI.
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# FALSE - Broadcast INIT-SIPI-SIPI.
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#
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# @Prompt BSP Broadcast Method for the first-time wakeup of APs
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gUefiCpuPkgTokenSpaceGuid.PcdFirstTimeWakeUpAPsBySipi|TRUE|BOOLEAN|0x30002007
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[PcdsFixedAtBuild, PcdsPatchableInModule]
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## This value is the CPU Local APIC base address, which aligns the address on a 4-KByte boundary.
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# @Prompt Configure base address of CPU Local APIC
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# @Expression 0x80000001 | (gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress & 0xfff) == 0
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gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress|0xfee00000|UINT32|0x00000001
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## Specifies delay value in microseconds after sending out an INIT IPI.
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# @Prompt Configure delay value after send an INIT IPI
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gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10000|UINT32|0x30000002
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## This value specifies the Application Processor (AP) stack size, used for Mp Service, which must
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## aligns the address on a 4-KByte boundary.
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# @Prompt Configure stack size for Application Processor (AP)
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gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x8000|UINT32|0x00000003
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## Specifies stack size in the temporary RAM. 0 means half of TemporaryRamSize.
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# @Prompt Stack size in the temporary RAM.
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gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0|UINT32|0x10001003
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## Specifies buffer size in bytes to save SMM profile data. The value should be a multiple of 4KB.
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# @Prompt SMM profile data buffer size.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileSize|0x200000|UINT32|0x32132107
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## Specifies stack size in bytes for each processor in SMM.
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# @Prompt Processor stack size in SMM.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x2000|UINT32|0x32132105
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## Specifies shadow stack size in bytes for each processor in SMM.
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# @Prompt Processor shadow stack size in SMM.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmShadowStackSize|0x2000|UINT32|0x3213210E
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## Indicates if SMM Code Access Check is enabled.
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# If enabled, the SMM handler cannot execute the code outside SMM regions.
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# This PCD is suggested to TRUE in production image.<BR><BR>
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# TRUE - SMM Code Access Check will be enabled.<BR>
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# FALSE - SMM Code Access Check will be disabled.<BR>
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# @Prompt SMM Code Access Check.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable|TRUE|BOOLEAN|0x60000013
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## Specifies the number of variable MTRRs reserved for OS use. The default number of
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# MTRRs reserved for OS use is 2.
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# @Prompt Number of reserved variable MTRRs.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0x2|UINT32|0x00000015
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## Specifies buffer size in bytes for STM exception stack. The value should be a multiple of 4KB.
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# @Prompt STM exception stack size.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStmExceptionStackSize|0x1000|UINT32|0x32132111
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## Specifies buffer size in bytes of MSEG. The value should be a multiple of 4KB.
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# @Prompt MSEG size.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize|0x200000|UINT32|0x32132112
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## Specifies the supported CPU features bit in array.
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# @Prompt Supported CPU features.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSupport|{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}|VOID*|0x00000016
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## Specifies if CPU features will be initialized after SMM relocation.
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# @Prompt If CPU features will be initialized after SMM relocation.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitAfterSmmRelocation|FALSE|BOOLEAN|0x0000001C
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## Specifies if CPU features will be initialized during S3 resume.
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# @Prompt If CPU features will be initialized during S3 resume.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume|FALSE|BOOLEAN|0x0000001D
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## Specifies CPUID Leaf 0x15 Time Stamp Counter and Nominal Core Crystal Clock Frequency.
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# TSC Frequency = ECX (core crystal clock frequency) * EBX/EAX.
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# Intel Xeon Processor Scalable Family with CPUID signature 06_55H = 25000000 (25MHz)
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# 6th and 7th generation Intel Core processors and Intel Xeon W Processor Family = 24000000 (24MHz)
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# Intel Atom processors based on Goldmont Microarchitecture with CPUID signature 06_5CH = 19200000 (19.2MHz)
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# @Prompt This PCD is the nominal frequency of the core crystal clock in Hz as is CPUID Leaf 0x15:ECX
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gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency|24000000|UINT64|0x32132113
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## Specifies the periodic interval value in microseconds for the status check
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# of APs for StartupAllAPs() and StartupThisAP() executed in non-blocking
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# mode in DXE phase.
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# @Prompt Periodic interval value in microseconds for AP status check in DXE.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuApStatusCheckIntervalInMicroSeconds|100000|UINT32|0x0000001E
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[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
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## Specifies max supported number of Logical Processors.
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# @Prompt Configure max supported number of Logical Processors
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gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|64|UINT32|0x00000002
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## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.
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# @Prompt Timeout for the BSP to detect all APs for the first time.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000|UINT32|0x00000004
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## Specifies the number of Logical Processors that are available in the
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# preboot environment after platform reset, including BSP and APs. Possible
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# values:<BR><BR>
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# zero (default) - PcdCpuBootLogicalProcessorNumber is ignored, and
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# PcdCpuApInitTimeOutInMicroSeconds limits the initial AP
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# detection by the BSP.<BR>
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# nonzero - PcdCpuApInitTimeOutInMicroSeconds is ignored. The initial
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# AP detection finishes only when the detected CPU count
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# (BSP plus APs) reaches the value of
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# PcdCpuBootLogicalProcessorNumber, regardless of how long
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# that takes.<BR>
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# @Prompt Number of Logical Processors available after platform reset.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber|0|UINT32|0x00000008
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## Specifies the base address of the first microcode Patch in the microcode Region.
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# @Prompt Microcode Region base address.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x00000005
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## Specifies the size of the microcode Region.
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# @Prompt Microcode Region size.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x00000006
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## Specifies the AP wait loop state during POST phase.
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# The value is defined as below.<BR><BR>
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# 1: Place AP in the Hlt-Loop state.<BR>
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# 2: Place AP in the Mwait-Loop state.<BR>
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# 3: Place AP in the Run-Loop state.<BR>
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# @Prompt The AP wait loop state.
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# @ValidRange 0x80000001 | 1 - 3
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gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|1|UINT8|0x60008006
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## Specifies the AP target C-state for Mwait during POST phase.
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# The default value 0 means C1 state.
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# The value is defined as below.<BR><BR>
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# @Prompt The specified AP target C-state for Mwait.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0|UINT8|0x00000007
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## Specifies timeout value in microseconds for the BSP in SMM to wait for all APs to come into SMM.
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# @Prompt AP synchronization timeout value in SMM.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000000|UINT64|0x32132104
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## Indicates the CPU synchronization method used when processing an SMI.
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# 0x00 - Traditional CPU synchronization method.<BR>
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# 0x01 - Relaxed CPU synchronization method.<BR>
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# @Prompt SMM CPU Synchronization Method.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode|0x00|UINT8|0x60000014
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## Specifies the On-demand clock modulation duty cycle when ACPI feature is enabled.
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# @Prompt The encoded values for target duty cycle modulation.
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# @ValidRange 0x80000001 | 0 - 15
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gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle|0x0|UINT8|0x0000001A
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## Indicates if the current boot is a power-on reset.<BR><BR>
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# TRUE - Current boot is a power-on reset.<BR>
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# FALSE - Current boot is not a power-on reset.<BR>
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# @Prompt Current boot is a power-on reset.
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gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset|FALSE|BOOLEAN|0x0000001B
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## This PCD indicates whether CPU processor trace is enabled on BSP only when CPU processor trace is enabled.<BR><BR>
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# This PCD is ignored if CPU processor trace is disabled.<BR><BR>
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# TRUE - CPU processor trace is enabled on BSP only.<BR>
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# FASLE - CPU processor trace is enabled on all CPU.<BR>
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# @Prompt Enable CPU processor trace only on BSP.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceBspOnly|FALSE|BOOLEAN|0x60000019
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## This PCD indicates if enable performance collecting when CPU processor trace is enabled.<BR><BR>
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# CYC/TSC timing packets will be generated to collect performance data if this PCD is TRUE.
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# This PCD is ignored if CPU processor trace is disabled.<BR><BR>
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# TRUE - Performance collecting will be enabled in processor trace.<BR>
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# FASLE - Performance collecting will be disabled in processor trace.<BR>
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# @Prompt Enable performance collecting when processor trace is enabled.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTracePerformanceCollecting|FALSE|BOOLEAN|0x60000020
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[PcdsFixedAtBuild.X64, PcdsPatchableInModule.X64, PcdsDynamic.X64, PcdsDynamicEx.X64]
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## Indicate access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.
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# MMIO access is always allowed regardless of the value of this PCD.
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# Loose of such restriction is only required by RAS components in X64 platforms.
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# The PCD value is considered as constantly TRUE in IA32 platforms.
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# When the PCD value is TRUE, page table is initialized to cover all memory spaces
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# and the memory occupied by page table is protected by page table itself as read-only.
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# In X64 build, it cannot be enabled at the same time with SMM profile feature (PcdCpuSmmProfileEnable).
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# In X64 build, it could not be enabled also at the same time with heap guard feature for SMM
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# (PcdHeapGuardPropertyMask in MdeModulePkg).
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# In IA32 build, page table memory is not marked as read-only when either SMM profile feature (PcdCpuSmmProfileEnable)
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# or heap guard feature for SMM (PcdHeapGuardPropertyMask in MdeModulePkg) is enabled.
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# TRUE - Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.<BR>
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# FALSE - Access to any type of non-SMRAM memory after SmmReadyToLock is allowed.<BR>
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# @Prompt Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F
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[PcdsDynamic, PcdsDynamicEx]
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## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.
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# @Prompt The pointer to a CPU S3 data buffer.
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# @ValidList 0x80000001 | 0
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gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0x0|UINT64|0x60000010
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## Contains the pointer to a CPU Hot Plug Data structure if CPU hot-plug is supported.
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# @Prompt The pointer to CPU Hot Plug Data.
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# @ValidList 0x80000001 | 0
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gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress|0x0|UINT64|0x60000011
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## Indicates processor feature capabilities, each bit corresponding to a specific feature.
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# @Prompt Processor feature capabilities.
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# @ValidList 0x80000001 | 0
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gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000018
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## As input, specifies user's desired settings for enabling/disabling processor features.
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## As output, specifies actual settings for processor features, each bit corresponding to a specific feature.
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# @Prompt As input, specifies user's desired processor feature settings. As output, specifies actual processor feature settings.
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# @ValidList 0x80000001 | 0
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gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000019
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## Contains the size of memory required when CPU processor trace is enabled.<BR><BR>
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# Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>
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# This PCD is ignored if CPU processor trace is disabled.<BR><BR>
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# Default value is 0x00 which means 4KB of memory is allocated if CPU processor trace is enabled.<BR>
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# 0x0 - 4K.<BR>
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# 0x1 - 8K.<BR>
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# 0x2 - 16K.<BR>
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# 0x3 - 32K.<BR>
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# 0x4 - 64K.<BR>
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# 0x5 - 128K.<BR>
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# 0x6 - 256K.<BR>
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# 0x7 - 512K.<BR>
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# 0x8 - 1M.<BR>
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# 0x9 - 2M.<BR>
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# 0xA - 4M.<BR>
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# 0xB - 8M.<BR>
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# 0xC - 16M.<BR>
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# 0xD - 32M.<BR>
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# 0xE - 64M.<BR>
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# 0xF - 128M.<BR>
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# @Prompt The memory size used for processor trace if processor trace is enabled.
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# @ValidRange 0x80000001 | 0 - 0xF
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gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize|0x0|UINT32|0x60000012
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## Contains the processor trace output scheme when CPU processor trace is enabled.<BR><BR>
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# Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>
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# This PCD is ignored if CPU processor trace is disabled.<BR><BR>
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# Default value is 0 which means single range output scheme will be used if CPU processor trace is enabled.<BR>
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# 0 - Single Range output scheme.<BR>
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# 1 - ToPA(Table of physical address) scheme.<BR>
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# @Prompt The processor trace output scheme used when processor trace is enabled.
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# @ValidRange 0x80000001 | 0 - 1
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gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x0|UINT8|0x60000015
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## This dynamic PCD indicates whether SEV-ES is enabled
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# TRUE - SEV-ES is enabled
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# FALSE - SEV-ES is not enabled
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# @Prompt SEV-ES Status
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gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|FALSE|BOOLEAN|0x60000016
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## This dynamic PCD contains the hypervisor features value obtained through the GHCB HYPERVISOR
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# features VMGEXIT defined in the version 2 of GHCB spec.
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# @Prompt GHCB Hypervisor Features
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gUefiCpuPkgTokenSpaceGuid.PcdGhcbHypervisorFeatures|0x0|UINT64|0x60000018
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[UserExtensions.TianoCore."ExtraFiles"]
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UefiCpuPkgExtra.uni
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