mirror of https://github.com/acidanthera/audk.git
348 lines
9.6 KiB
Plaintext
348 lines
9.6 KiB
Plaintext
/** @file
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Contains root level name space objects for the platform
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Copyright (c) 2013-2019 Intel Corporation.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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//
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// OS TYPE DEFINITION
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//
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#define WINDOWS_XP 0x01
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#define WINDOWS_XP_SP1 0x02
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#define WINDOWS_XP_SP2 0x04
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#define WINDOWS_2003 0x08
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#define WINDOWS_Vista 0x10
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#define WINDOWS_WIN7 0x11
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#define WINDOWS_WIN8 0x12
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#define WINDOWS_WIN8_1 0x13
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#define LINUX 0xF0
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//
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// GPIO Interrupt Connection Resource Descriptor (GpioInt) usage.
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// GpioInt() descriptors maybe used in this file and included .asi files.
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//
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// The mapping below was provided by the first OS user that requested
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// GpioInt() support.
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// Other OS users that need GpioInt() support must use the following mapping.
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//
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#define QUARK_GPIO8_MAPPING 0x00
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#define QUARK_GPIO9_MAPPING 0x01
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#define QUARK_GPIO_SUS0_MAPPING 0x02
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#define QUARK_GPIO_SUS1_MAPPING 0x03
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#define QUARK_GPIO_SUS2_MAPPING 0x04
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#define QUARK_GPIO_SUS3_MAPPING 0x05
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#define QUARK_GPIO_SUS4_MAPPING 0x06
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#define QUARK_GPIO_SUS5_MAPPING 0x07
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#define QUARK_GPIO0_MAPPING 0x08
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#define QUARK_GPIO1_MAPPING 0x09
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#define QUARK_GPIO2_MAPPING 0x0A
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#define QUARK_GPIO3_MAPPING 0x0B
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#define QUARK_GPIO4_MAPPING 0x0C
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#define QUARK_GPIO5_MAPPING 0x0D
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#define QUARK_GPIO6_MAPPING 0x0E
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#define QUARK_GPIO7_MAPPING 0x0F
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DefinitionBlock (
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"Platform.aml",
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"DSDT",
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1,
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"INTEL ",
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"QuarkNcS",
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3)
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{
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//
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// Global Variables
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//
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Name(\GPIC, 0x0)
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//
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// Port 80
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//
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OperationRegion (DBG0, SystemIO, 0x80, 1)
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Field (DBG0, ByteAcc, NoLock, Preserve)
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{ IO80,8 }
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//
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// Access CMOS range
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//
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OperationRegion (ACMS, SystemIO, 0x72, 2)
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Field (ACMS, ByteAcc, NoLock, Preserve)
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{ INDX, 8, DATA, 8 }
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//
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// Global NVS Memory Block
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//
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OperationRegion (MNVS, SystemMemory, 0xFFFF0000, 512)
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Field (MNVS, ByteAcc, NoLock, Preserve)
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{
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OSTP, 32,
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CFGD, 32,
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HPEA, 32, // HPET Enabled ?
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P1BB, 32, // Pm1blkIoBaseAddress;
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PBAB, 32, // PmbaIoBaseAddress;
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GP0B, 32, // Gpe0blkIoBaseAddress;
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GPAB, 32, // GbaIoBaseAddress;
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SMBB, 32, // SmbaIoBaseAddress;
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NRV1, 32, // GNVS reserved field 1.
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WDTB, 32, // WdtbaIoBaseAddress;
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HPTB, 32, // HpetBaseAddress;
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HPTS, 32, // HpetSize;
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PEXB, 32, // PciExpressBaseAddress;
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PEXS, 32, // PciExpressSize;
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RCBB, 32, // RcbaMmioBaseAddress;
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RCBS, 32, // RcbaMmioSize;
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APCB, 32, // IoApicBaseAddress;
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APCS, 32, // IoApicSize;
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TPMP, 32, // TpmPresent ?
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DBGP, 32, // DBG2 Present?
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PTYP, 32, // Set to one of EFI_PLATFORM_TYPE enums.
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ALTS, 32, // Use alternate I2c SLA addresses.
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}
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OperationRegion (GPEB, SystemIO, 0x1100, 0x40) //GPE Block
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Field (GPEB, AnyAcc, NoLock, Preserve)
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{
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Offset(0x10),
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SMIE, 32, // SMI Enable
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SMIS, 32, // SMI Status
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}
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//
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// Processor Objects
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//
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Scope(\_PR) {
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//
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// IO base will be updated at runtime with search key "PRIO"
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//
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Processor (CPU0, 0x01, 0x4F495250, 0x06) {}
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}
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//
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// System Sleep States
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//
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Name (\_S0,Package (){0,0,0,0})
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Name (\_S3,Package (){5,0,0,0})
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Name (\_S4,Package (){6,0,0,0})
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Name (\_S5,Package (){7,0,0,0})
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//
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// General Purpose Event
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//
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Scope(\_GPE)
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{
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//
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// EGPE generated GPE
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//
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Method(_L0D, 0x0, NotSerialized)
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{
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//
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// Check EGPE for this wake event
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//
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Notify (\_SB.SLPB, 0x02)
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}
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//
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// GPIO generated GPE
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//
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Method(_L0E, 0x0, NotSerialized)
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{
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//
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// Check GPIO for this wake event
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//
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Notify (\_SB.PWRB, 0x02)
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}
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//
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// SCLT generated GPE
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//
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Method(_L0F, 0x0, NotSerialized)
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{
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//
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// Check SCLT for this wake event
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//
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Notify (\_SB.PCI0.SDIO, 0x02)
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Notify (\_SB.PCI0.URT0, 0x02)
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Notify (\_SB.PCI0.USBD, 0x02)
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Notify (\_SB.PCI0.EHCI, 0x02)
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Notify (\_SB.PCI0.OHCI, 0x02)
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Notify (\_SB.PCI0.URT1, 0x02)
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Notify (\_SB.PCI0.ENT0, 0x02)
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Notify (\_SB.PCI0.ENT1, 0x02)
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Notify (\_SB.PCI0.SPI0, 0x02)
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Notify (\_SB.PCI0.SPI1, 0x02)
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Notify (\_SB.PCI0.GIP0, 0x02)
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}
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//
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// Remote Management Unit generated GPE
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//
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Method(_L10, 0x0, NotSerialized)
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{
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//
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// Check Remote Management Unit for this wake event.
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//
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}
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//
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// PCIE generated GPE
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//
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Method(_L11, 0x0, NotSerialized)
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{
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//
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// Check PCIE for this wake event
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//
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Notify (\_SB.PCI0.PEX0, 0x02)
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Notify (\_SB.PCI0.PEX1, 0x02)
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}
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}
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//
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// define Sleeping button as mentioned in ACPI spec 2.0
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//
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Device (\_SB.SLPB)
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{
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Name (_HID, EISAID ("PNP0C0E"))
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Method (_PRW, 0, NotSerialized)
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{
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Return (Package (0x02) {0x0D,0x04})
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}
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}
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//
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// define Power Button
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//
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Device (\_SB.PWRB)
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{
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Name (_HID, EISAID ("PNP0C0C"))
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Method (_PRW, 0, NotSerialized)
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{
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Return (Package (0x02) {0x0E,0x04})
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}
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}
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//
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// System Wake up
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//
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Method(_WAK, 1, Serialized)
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{
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// Do nothing here
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Return (0)
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}
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//
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// System sleep down
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//
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Method (_PTS, 1, NotSerialized)
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{
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// Get ready for S3 sleep
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if (Lequal(Arg0,3))
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{
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Store(0xffffffff,SMIS) // clear SMI status
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Store(SMIE, Local0) // SMI Enable
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Or(Local0,0x4,SMIE) // Generate SMI on sleep
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}
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}
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//
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// Determing PIC mode
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//
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Method(\_PIC, 1, NotSerialized)
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{
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Store(Arg0,\GPIC)
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}
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//
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// System Bus
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//
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Scope(\_SB)
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{
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Device(PCI0)
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{
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Name(_HID,EISAID ("PNP0A08")) // PCI Express Root Bridge
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Name(_CID,EISAID ("PNP0A03")) // Compatible PCI Root Bridge
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Name(_ADR,0x00000000) // Device (HI WORD)=0, Func (LO WORD)=0
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Method (_INI)
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{
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Store(LINUX, OSTP) // Set the default os is Linux
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If (CondRefOf (_OSI))
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{
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//
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//_OSI is supported, so it is WinXp or Win2003Server
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//
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If (\_OSI("Windows 2001"))
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{
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Store (WINDOWS_XP, OSTP)
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}
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If (\_OSI("Windows 2001 SP1"))
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{
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Store (WINDOWS_XP_SP1, OSTP)
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}
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If (\_OSI("Windows 2001 SP2"))
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{
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Store (WINDOWS_XP_SP2, OSTP)
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}
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If (\_OSI("Windows 2001.1"))
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{
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Store (WINDOWS_2003, OSTP)
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}
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If (\_OSI("Windows 2006"))
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{
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Store (WINDOWS_Vista, OSTP)
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}
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If (\_OSI("Windows 2009"))
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{
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Store (WINDOWS_WIN7, OSTP)
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}
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If (\_OSI("Windows 2012"))
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{
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Store (WINDOWS_WIN8, OSTP)
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}
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If (\_OSI("Windows 2013"))
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{
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Store (WINDOWS_WIN8_1, OSTP)
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}
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If (\_OSI("Linux"))
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{
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Store (LINUX, OSTP)
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}
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}
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}
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Include ("PciHostBridge.asi") // PCI0 Host bridge
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Include ("QNC.asi") // QNC miscellaneous
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Include ("PcieExpansionPrt.asi") // PCIe expansion bridges/devices
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Include ("QuarkSouthCluster.asi") // Quark South Cluster devices
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Include ("QNCLpc.asi") // LPC bridge device
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Include ("QNCApic.asi") // QNC I/O Apic device
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}
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//
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// Include asi files for I2C and SPI onboard devices.
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// Devices placed here instead of below relevant controllers.
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// Hardware topology information is maintained by the
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// ResourceSource arg to the I2CSerialBus/SPISerialBus macros
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// within the device asi files.
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//
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Include ("Tpm.asi") // TPM device.
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Include ("CY8C9540A.asi") // CY8C9540A 40Bit I/O Expander & EEPROM
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Include ("PCAL9555A.asi") // NXP PCAL9555A I/O expander.
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Include ("PCA9685.asi") // NXP PCA9685 PWM/LED controller.
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Include ("CAT24C08.asi") // ONSEMI CAT24C08 I2C 8KB EEPROM.
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Include ("AD7298.asi") // Analog devices AD7298 ADC.
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Include ("ADC108S102.asi") // TI ADC108S102 ADC.
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Include ("GpioClient.asi") // Software device to expose GPIO
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}
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}
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