mirror of https://github.com/acidanthera/audk.git
482 lines
12 KiB
C
482 lines
12 KiB
C
/** @file
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Helper routines with common PEI / DXE implementation.
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Copyright (c) 2013-2016 Intel Corporation.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "CommonHeader.h"
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#include <Library/I2cLib.h>
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CHAR16 *mPlatTypeNameTable[] = { EFI_PLATFORM_TYPE_NAME_TABLE_DEFINITION };
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UINTN mPlatTypeNameTableLen = ((sizeof(mPlatTypeNameTable)) / sizeof (CHAR16 *));
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//
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// Routines defined in other source modules of this component.
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//
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//
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// Routines local to this source module.
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//
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//
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// Routines shared with other souce modules in this component.
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//
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EFI_STATUS
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WriteFirstFreeSpiProtect (
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IN CONST UINT32 PchRootComplexBar,
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IN CONST UINT32 DirectValue,
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IN CONST UINT32 BaseAddress,
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IN CONST UINT32 Length,
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OUT UINT32 *OffsetPtr
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)
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{
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UINT32 RegVal;
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UINT32 Offset;
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UINT32 StepLen;
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ASSERT (PchRootComplexBar > 0);
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Offset = 0;
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if (OffsetPtr != NULL) {
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*OffsetPtr = Offset;
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}
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if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0) == 0) {
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Offset = R_QNC_RCRB_SPIPBR0;
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} else {
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if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR1) == 0) {
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Offset = R_QNC_RCRB_SPIPBR1;
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} else {
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if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR2) == 0) {
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Offset = R_QNC_RCRB_SPIPBR2;
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}
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}
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}
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if (Offset != 0) {
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if (DirectValue == 0) {
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StepLen = ALIGN_VALUE (Length,SIZE_4KB); // Bring up to 4K boundary.
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RegVal = BaseAddress + StepLen - 1;
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RegVal &= 0x00FFF000; // Set EDS Protected Range Limit (PRL).
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RegVal |= ((BaseAddress >> 12) & 0xfff); // or in EDS Protected Range Base (PRB).
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} else {
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RegVal = DirectValue;
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}
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//
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// Enable protection.
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//
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RegVal |= B_QNC_RCRB_SPIPBRn_WPE;
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MmioWrite32 (PchRootComplexBar + Offset, RegVal);
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if (RegVal == MmioRead32 (PchRootComplexBar + Offset)) {
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if (OffsetPtr != NULL) {
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*OffsetPtr = Offset;
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}
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return EFI_SUCCESS;
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}
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return EFI_DEVICE_ERROR;
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}
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return EFI_NOT_FOUND;
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}
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//
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// Routines exported by this component.
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//
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/**
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Clear SPI Protect registers.
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@retval EFI_SUCCESS SPI protect registers cleared.
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@retval EFI_ACCESS_DENIED Unable to clear SPI protect registers.
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**/
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EFI_STATUS
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EFIAPI
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PlatformClearSpiProtect (
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VOID
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)
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{
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UINT32 PchRootComplexBar;
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PchRootComplexBar = QNC_RCRB_BASE;
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//
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// Check if the SPI interface has been locked-down.
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//
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if ((MmioRead16 (PchRootComplexBar + R_QNC_RCRB_SPIS) & B_QNC_RCRB_SPIS_SCL) != 0) {
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return EFI_ACCESS_DENIED;
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}
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MmioWrite32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0, 0);
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if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0) != 0) {
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return EFI_ACCESS_DENIED;
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}
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MmioWrite32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR1, 0);
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if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0) != 0) {
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return EFI_ACCESS_DENIED;
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}
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MmioWrite32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR2, 0);
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if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0) != 0) {
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return EFI_ACCESS_DENIED;
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}
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return EFI_SUCCESS;
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}
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/**
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Determine if an SPI address range is protected.
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@param SpiBaseAddress Base of SPI range.
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@param Length Length of SPI range.
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@retval TRUE Range is protected.
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@retval FALSE Range is not protected.
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**/
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BOOLEAN
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EFIAPI
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PlatformIsSpiRangeProtected (
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IN CONST UINT32 SpiBaseAddress,
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IN CONST UINT32 Length
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)
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{
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UINT32 RegVal;
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UINT32 Offset;
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UINT32 Limit;
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UINT32 ProtectedBase;
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UINT32 ProtectedLimit;
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UINT32 PchRootComplexBar;
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PchRootComplexBar = QNC_RCRB_BASE;
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if (Length > 0) {
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Offset = R_QNC_RCRB_SPIPBR0;
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Limit = SpiBaseAddress + (Length - 1);
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do {
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RegVal = MmioRead32 (PchRootComplexBar + Offset);
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if ((RegVal & B_QNC_RCRB_SPIPBRn_WPE) != 0) {
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ProtectedBase = (RegVal & 0xfff) << 12;
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ProtectedLimit = (RegVal & 0x00fff000) + 0xfff;
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if (SpiBaseAddress >= ProtectedBase && Limit <= ProtectedLimit) {
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return TRUE;
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}
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}
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if (Offset == R_QNC_RCRB_SPIPBR0) {
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Offset = R_QNC_RCRB_SPIPBR1;
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} else if (Offset == R_QNC_RCRB_SPIPBR1) {
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Offset = R_QNC_RCRB_SPIPBR2;
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} else {
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break;
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}
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} while (TRUE);
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}
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return FALSE;
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}
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/**
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Set Legacy GPIO Level
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@param LevelRegOffset GPIO level register Offset from GPIO Base Address.
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@param GpioNum GPIO bit to change.
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@param HighLevel If TRUE set GPIO High else Set GPIO low.
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**/
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VOID
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EFIAPI
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PlatformLegacyGpioSetLevel (
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IN CONST UINT32 LevelRegOffset,
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IN CONST UINT32 GpioNum,
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IN CONST BOOLEAN HighLevel
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)
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{
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UINT32 RegValue;
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UINT32 GpioBaseAddress;
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UINT32 GpioNumMask;
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GpioBaseAddress = LpcPciCfg32 (R_QNC_LPC_GBA_BASE) & B_QNC_LPC_GPA_BASE_MASK;
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ASSERT (GpioBaseAddress > 0);
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RegValue = IoRead32 (GpioBaseAddress + LevelRegOffset);
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GpioNumMask = (1 << GpioNum);
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if (HighLevel) {
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RegValue |= (GpioNumMask);
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} else {
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RegValue &= ~(GpioNumMask);
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}
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IoWrite32 (GpioBaseAddress + LevelRegOffset, RegValue);
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}
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/**
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Get Legacy GPIO Level
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@param LevelRegOffset GPIO level register Offset from GPIO Base Address.
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@param GpioNum GPIO bit to check.
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@retval TRUE If bit is SET.
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@retval FALSE If bit is CLEAR.
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**/
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BOOLEAN
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EFIAPI
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PlatformLegacyGpioGetLevel (
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IN CONST UINT32 LevelRegOffset,
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IN CONST UINT32 GpioNum
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)
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{
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UINT32 RegValue;
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UINT32 GpioBaseAddress;
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UINT32 GpioNumMask;
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GpioBaseAddress = LpcPciCfg32 (R_QNC_LPC_GBA_BASE) & B_QNC_LPC_GPA_BASE_MASK;
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RegValue = IoRead32 (GpioBaseAddress + LevelRegOffset);
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GpioNumMask = (1 << GpioNum);
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return ((RegValue & GpioNumMask) != 0);
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}
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BOOLEAN
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Pcal9555GetPortRegBit (
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IN CONST UINT32 Pcal9555SlaveAddr,
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IN CONST UINT32 GpioNum,
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IN CONST UINT8 RegBase
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)
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{
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EFI_STATUS Status;
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UINTN ReadLength;
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UINTN WriteLength;
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UINT8 Data[2];
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EFI_I2C_DEVICE_ADDRESS I2cDeviceAddr;
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EFI_I2C_ADDR_MODE I2cAddrMode;
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UINT8 *RegValuePtr;
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UINT8 GpioNumMask;
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UINT8 SubAddr;
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I2cDeviceAddr.I2CDeviceAddress = (UINTN)Pcal9555SlaveAddr;
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I2cAddrMode = EfiI2CSevenBitAddrMode;
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if (GpioNum < 8) {
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SubAddr = RegBase;
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GpioNumMask = (UINT8)(1 << GpioNum);
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} else {
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SubAddr = RegBase + 1;
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GpioNumMask = (UINT8)(1 << (GpioNum - 8));
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}
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//
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// Output port value always at 2nd byte in Data variable.
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//
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RegValuePtr = &Data[1];
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//
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// On read entry sub address at 2nd byte, on read exit output
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// port value in 2nd byte.
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//
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Data[1] = SubAddr;
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WriteLength = 1;
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ReadLength = 1;
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Status = I2cReadMultipleByte (
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I2cDeviceAddr,
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I2cAddrMode,
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&WriteLength,
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&ReadLength,
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&Data[1]
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);
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ASSERT_EFI_ERROR (Status);
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//
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// Adjust output port bit given callers request.
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//
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return ((*RegValuePtr & GpioNumMask) != 0);
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}
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VOID
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Pcal9555SetPortRegBit (
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IN CONST UINT32 Pcal9555SlaveAddr,
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IN CONST UINT32 GpioNum,
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IN CONST UINT8 RegBase,
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IN CONST BOOLEAN LogicOne
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)
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{
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EFI_STATUS Status;
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UINTN ReadLength;
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UINTN WriteLength;
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UINT8 Data[2];
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EFI_I2C_DEVICE_ADDRESS I2cDeviceAddr;
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EFI_I2C_ADDR_MODE I2cAddrMode;
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UINT8 *RegValuePtr;
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UINT8 GpioNumMask;
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UINT8 SubAddr;
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I2cDeviceAddr.I2CDeviceAddress = (UINTN)Pcal9555SlaveAddr;
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I2cAddrMode = EfiI2CSevenBitAddrMode;
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if (GpioNum < 8) {
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SubAddr = RegBase;
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GpioNumMask = (UINT8)(1 << GpioNum);
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} else {
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SubAddr = RegBase + 1;
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GpioNumMask = (UINT8)(1 << (GpioNum - 8));
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}
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//
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// Output port value always at 2nd byte in Data variable.
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//
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RegValuePtr = &Data[1];
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//
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// On read entry sub address at 2nd byte, on read exit output
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// port value in 2nd byte.
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//
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Data[1] = SubAddr;
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WriteLength = 1;
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ReadLength = 1;
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Status = I2cReadMultipleByte (
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I2cDeviceAddr,
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I2cAddrMode,
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&WriteLength,
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&ReadLength,
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&Data[1]
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);
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ASSERT_EFI_ERROR (Status);
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//
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// Adjust output port bit given callers request.
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//
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if (LogicOne) {
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*RegValuePtr = *RegValuePtr | GpioNumMask;
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} else {
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*RegValuePtr = *RegValuePtr & ~(GpioNumMask);
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}
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//
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// Update register. Sub address at 1st byte, value at 2nd byte.
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//
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WriteLength = 2;
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Data[0] = SubAddr;
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Status = I2cWriteMultipleByte (
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I2cDeviceAddr,
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I2cAddrMode,
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&WriteLength,
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Data
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);
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ASSERT_EFI_ERROR (Status);
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}
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/**
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Set the direction of Pcal9555 IO Expander GPIO pin.
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@param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.
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@param GpioNum Gpio direction to configure - values 0-7 for Port0
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and 8-15 for Port1.
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@param CfgAsInput If TRUE set pin direction as input else set as output.
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**/
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VOID
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EFIAPI
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PlatformPcal9555GpioSetDir (
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IN CONST UINT32 Pcal9555SlaveAddr,
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IN CONST UINT32 GpioNum,
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IN CONST BOOLEAN CfgAsInput
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)
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{
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Pcal9555SetPortRegBit (
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Pcal9555SlaveAddr,
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GpioNum,
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PCAL9555_REG_CFG_PORT0,
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CfgAsInput
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);
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}
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/**
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Set the level of Pcal9555 IO Expander GPIO high or low.
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@param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.
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@param GpioNum Gpio to change values 0-7 for Port0 and 8-15
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for Port1.
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@param HighLevel If TRUE set pin high else set pin low.
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**/
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VOID
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EFIAPI
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PlatformPcal9555GpioSetLevel (
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IN CONST UINT32 Pcal9555SlaveAddr,
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IN CONST UINT32 GpioNum,
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IN CONST BOOLEAN HighLevel
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)
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{
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Pcal9555SetPortRegBit (
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Pcal9555SlaveAddr,
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GpioNum,
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PCAL9555_REG_OUT_PORT0,
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HighLevel
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);
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}
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/**
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Enable pull-up/pull-down resistors of Pcal9555 GPIOs.
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@param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.
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@param GpioNum Gpio to change values 0-7 for Port0 and 8-15
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for Port1.
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**/
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VOID
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EFIAPI
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PlatformPcal9555GpioEnablePull (
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IN CONST UINT32 Pcal9555SlaveAddr,
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IN CONST UINT32 GpioNum
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)
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{
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Pcal9555SetPortRegBit (
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Pcal9555SlaveAddr,
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GpioNum,
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PCAL9555_REG_PULL_EN_PORT0,
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TRUE
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);
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}
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/**
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Disable pull-up/pull-down resistors of Pcal9555 GPIOs.
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@param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.
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@param GpioNum Gpio to change values 0-7 for Port0 and 8-15
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for Port1.
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**/
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VOID
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EFIAPI
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PlatformPcal9555GpioDisablePull (
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IN CONST UINT32 Pcal9555SlaveAddr,
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IN CONST UINT32 GpioNum
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)
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{
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Pcal9555SetPortRegBit (
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Pcal9555SlaveAddr,
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GpioNum,
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PCAL9555_REG_PULL_EN_PORT0,
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FALSE
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);
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}
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/**
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Get state of Pcal9555 GPIOs.
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@param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.
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@param GpioNum Gpio to change values 0-7 for Port0 and 8-15
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for Port1.
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@retval TRUE GPIO pin is high
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@retval FALSE GPIO pin is low
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**/
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BOOLEAN
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EFIAPI
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PlatformPcal9555GpioGetState (
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IN CONST UINT32 Pcal9555SlaveAddr,
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IN CONST UINT32 GpioNum
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)
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{
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return Pcal9555GetPortRegBit (Pcal9555SlaveAddr, GpioNum, PCAL9555_REG_IN_PORT0);
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}
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