mirror of https://github.com/acidanthera/audk.git
141 lines
3.9 KiB
C
141 lines
3.9 KiB
C
/** @file
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Do platform initialization for PCI bridge.
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Copyright (c) 2013-2015 Intel Corporation.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PciHostBridge.h"
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo;
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EFI_STATUS
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ChipsetPreprocessController (
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IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
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IN EFI_HANDLE RootBridgeHandle,
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
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IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
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)
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/*++
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Routine Description:
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This function is called for all the PCI controllers that the PCI
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bus driver finds. Can be used to Preprogram the controller.
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Arguments:
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This -- The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance
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RootBridgeHandle -- The PCI Root Bridge handle
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PciBusAddress -- Address of the controller on the PCI bus
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Phase -- The Phase during resource allocation
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Returns:
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EFI_SUCCESS
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--*/
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// GC_TODO: PciAddress - add argument and description to function comment
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//
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// GC_TODO: PciAddress - add argument and description to function comment
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//
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// GC_TODO: PciAddress - add argument and description to function comment
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//
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// GC_TODO: PciAddress - add argument and description to function comment
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//
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{
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EFI_STATUS Status;
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UINT8 Latency;
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UINT8 CacheLineSize;
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if (mPciRootBridgeIo == NULL) {
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//
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// Get root bridge in the system.
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//
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Status = gBS->HandleProtocol (RootBridgeHandle, &gEfiPciRootBridgeIoProtocolGuid, (VOID **) &mPciRootBridgeIo);
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ASSERT_EFI_ERROR (Status);
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}
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if (Phase == EfiPciBeforeResourceCollection) {
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//
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// Program the latency register, CLS register
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//
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PciAddress.Register = PCI_LATENCY_TIMER_OFFSET;
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mPciRootBridgeIo->Pci.Read (
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mPciRootBridgeIo,
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EfiPciWidthUint8,
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*((UINT64 *) &PciAddress),
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1,
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&Latency
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);
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//
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// PCI-x cards come up with a default latency of 0x40. Don't touch them.
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//
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if (Latency == 0) {
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Latency = DEFAULT_PCI_LATENCY;
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mPciRootBridgeIo->Pci.Write (
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mPciRootBridgeIo,
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EfiPciWidthUint8,
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*((UINT64 *) &PciAddress),
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1,
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&Latency
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);
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}
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//
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// Program Cache Line Size as 64bytes
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// 16 of DWORDs = 64bytes (0x10)
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//
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PciAddress.Register = PCI_CACHELINE_SIZE_OFFSET;
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CacheLineSize = 0x10;
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mPciRootBridgeIo->Pci.Write (
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mPciRootBridgeIo,
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EfiPciWidthUint8,
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*((UINT64 *) &PciAddress),
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1,
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&CacheLineSize
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);
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}
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return EFI_SUCCESS;
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}
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UINT64
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GetAllocAttributes (
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IN UINTN RootBridgeIndex
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)
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/*++
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Routine Description:
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Returns the Allocation attributes for the BNB Root Bridge.
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Arguments:
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RootBridgeIndex - The root bridge number. 0 based.
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Returns:
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EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | EFI_PCI_HOST_BRIDGE_MEM64_DECODE
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--*/
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{
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//
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// Cannot have more than one Root bridge
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//
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//ASSERT (RootBridgeIndex == 0);
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//
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// PCI Root Bridge does not support separate windows for Non-prefetchable
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// and Prefetchable memory. A PCI bus driver needs to include requests for
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// Prefetchable memory in the Non-prefetchable memory pool.
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// Further TNB does not support 64 bit memory apertures for PCI. BNB
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// can only have system memory above 4 GB,
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//
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return EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | EFI_PCI_HOST_BRIDGE_MEM64_DECODE;
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}
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