mirror of https://github.com/acidanthera/audk.git
181 lines
7.5 KiB
C
181 lines
7.5 KiB
C
/*++
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Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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Module Name:
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PlatformCpuInfo.h
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Abstract:
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GUID used for Platform CPU Info Data entries in the HOB list.
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--*/
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#ifndef _PLATFORM_CPU_INFO_GUID_H_
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#define _PLATFORM_CPU_INFO_GUID_H_
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#include "CpuType.h"
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#include <Library/CpuIA32.h>
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#define EFI_PLATFORM_CPU_INFO_GUID \
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{\
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0xbb9c7ab7, 0xb8d9, 0x4bf3, 0x9c, 0x29, 0x9b, 0xf3, 0x41, 0xe2, 0x17, 0xbc \
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}
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extern EFI_GUID gEfiPlatformCpuInfoGuid;
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extern CHAR16 EfiPlatformCpuInfoVariable[];
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//
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// Tri-state for feature capabilities and enable/disable.
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// [0] clear=feature isn't capable
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// [0] set =feature is capable
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// [1] clear=feature is disabled
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// [1] set =feature is enabled
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//
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#define CPU_FEATURES_CAPABLE BIT0
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#define CPU_FEATURES_ENABLE BIT1
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#define MAX_CACHE_DESCRIPTORS 64
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#define MAXIMUM_CPU_BRAND_STRING_LENGTH 48
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#pragma pack(1)
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typedef struct {
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UINT32 FullCpuId; // [31:0] & 0x0FFF0FFF
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UINT32 FullFamilyModelId; // [31:0] & 0x0FFF0FF0
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UINT8 ExtendedFamilyId; // [27:20]
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UINT8 ExtendedModelId; // [19:16]
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UINT8 ProcessorType; // [13:11]
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UINT8 FamilyId; // [11:8]
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UINT8 Model; // [7:4]
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UINT8 SteppingId; // [3:0]
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} EFI_CPU_VERSION_INFO; // CPUID.1.EAX
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typedef struct {
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UINT32 L1InstructionCacheSize;
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UINT32 L1DataCacheSize;
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UINT32 L2CacheSize;
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UINT32 L3CacheSize;
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UINT32 TraceCacheSize;
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UINT8 CacheDescriptor[MAX_CACHE_DESCRIPTORS];
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} EFI_CPU_CACHE_INFO; // CPUID.2.EAX
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typedef struct {
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UINT8 PhysicalPackages;
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UINT8 LogicalProcessorsPerPhysicalPackage;
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UINT8 CoresPerPhysicalPackage;
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UINT8 ThreadsPerCore;
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} EFI_CPU_PACKAGE_INFO; // CPUID.4.EAX
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typedef struct {
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UINT32 RegEdx; // CPUID.5.EAX
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UINT8 MaxCState;
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UINT8 C0SubCStatesMwait; // EDX [3:0]
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UINT8 C1SubCStatesMwait; // EDX [7:4]
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UINT8 C2SubCStatesMwait; // EDX [11:8]
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UINT8 C3SubCStatesMwait; // EDX [15:12]
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UINT8 C4SubCStatesMwait; // EDX [19:16]
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UINT8 C5SubCStatesMwait; // EDX [23:20]
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UINT8 C6SubCStatesMwait; // EDX [27:24]
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UINT8 C7SubCStatesMwait; // EDX [31:28]
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UINT8 MonitorMwaitSupport; // ECX [0]
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UINT8 InterruptsBreakMwait; // ECX [1]
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} EFI_CPU_CSTATE_INFO; // CPUID.5.EAX
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typedef struct {
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UINT8 Turbo; // EAX [1]
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UINT8 PECI; // EAX [0]
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UINT8 NumIntThresholds; // EBX [3:0]
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UINT8 HwCoordinationFeedback; // ECX [0]
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} EFI_CPU_POWER_MANAGEMENT; // CPUID.6.EAX
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//
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// IMPORTANT: Each CPU feature enabling entry is assumed a tri-state variable.
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// - Keep the respective feature entry variable as default value (0x00)
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// if the CPU is not capable for the feature.
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// - Use the specially defined programming convention to update the variable
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// to indicate capable, enable or disable.
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// ie. F_CAPABLE for feature available
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// F_ENABLE for feature enable
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// F_DISABLE for feature disable
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//
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typedef struct {
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EFI_CPUID_REGISTER Regs; // CPUID.1.EAX
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UINT8 Xapic; // ECX [21]
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UINT8 SSE4_2; // ECX [20]
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UINT8 SSE4_1; // ECX [19]
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UINT8 Dca; // ECX [18]
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UINT8 SupSSE3; // ECX [9]
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UINT8 Tm2; // ECX [8]
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UINT8 Eist; // ECX [7]
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UINT8 Lt; // ECX [6]
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UINT8 Vt; // ECX [5]
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UINT8 Mwait; // ECX [3]
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UINT8 SSE3; // ECX [0]
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UINT8 Tcc; // EDX [29]
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UINT8 Mt; // EDX [28]
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UINT8 SSE2; // EDX [26]
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UINT8 SSE; // EDX [25]
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UINT8 MMX; // EDX [23]
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EFI_CPUID_REGISTER ExtRegs; // CPUID.80000001.EAX
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UINT8 ExtLahfSahf64; // ECX [0]
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UINT8 ExtIntel64; // EDX [29]
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UINT8 ExtXd; // EDX [20]
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UINT8 ExtSysCallRet64; // EDX [11]
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UINT16 Ht; // CPUID.0B.EAX EBX [15:0]
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} EFI_CPU_FEATURES; // CPUID.1.EAX, CPUID.0B.EAX, CPUID.80000001.EAX
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typedef struct {
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UINT8 PhysicalBits;
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UINT8 VirtualBits;
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} EFI_CPU_ADDRESS_BITS; // CPUID.80000008.EAX
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typedef struct {
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UINT8 PlatformID; // MSR 0x17 [52:50]
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UINT32 MicrocodeRevision; // MSR 0x8B [63:32]
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UINT8 MaxEfficiencyRatio; // MSR 0xCE [47:40]
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UINT8 DdrRatioUnlockCap; // MSR 0xCE [30]
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UINT8 TdcTdpLimitsTurbo; // MSR 0xCE [29]
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UINT8 RatioLimitsTurbo; // MSR 0xCE [28]
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UINT8 PreProduction; // MSR 0xCE [27]
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UINT8 DcuModeSelect; // MSR 0xCE [26]
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UINT8 MaxNonTurboRatio; // MSR 0xCE [15:8]
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UINT8 Emrr; // MSR 0xFE [12]
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UINT8 Smrr; // MSR 0xFE [11]
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UINT8 VariableMtrrCount; // MSR 0xFE [7:0]
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UINT16 PState; // MSR 0x198 [15:0]
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UINT8 TccActivationTemperature; // MSR 0x1A2 [23:16]
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UINT8 TemperatureControlOffset; // MSR 0x1A2 [15:8]
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UINT32 PCIeBar; // MSR 0x300 [39:20]
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UINT8 PCIeBarSizeMB; // MSR 0x300 [3:1]
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} EFI_MSR_FEATURES;
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typedef struct {
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BOOLEAN IsIntelProcessor;
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UINT8 BrandString[MAXIMUM_CPU_BRAND_STRING_LENGTH + 1];
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UINT32 CpuidMaxInputValue;
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UINT32 CpuidMaxExtInputValue;
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EFI_CPU_UARCH CpuUarch;
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EFI_CPU_FAMILY CpuFamily;
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EFI_CPU_PLATFORM CpuPlatform;
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EFI_CPU_TYPE CpuType;
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EFI_CPU_VERSION_INFO CpuVersion;
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EFI_CPU_CACHE_INFO CpuCache;
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EFI_CPU_FEATURES CpuFeatures;
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EFI_CPU_CSTATE_INFO CpuCState;
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EFI_CPU_PACKAGE_INFO CpuPackage;
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EFI_CPU_POWER_MANAGEMENT CpuPowerManagement;
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EFI_CPU_ADDRESS_BITS CpuAddress;
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EFI_MSR_FEATURES Msr;
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} EFI_PLATFORM_CPU_INFO;
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#pragma pack()
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#endif
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