mirror of https://github.com/acidanthera/audk.git
736 lines
25 KiB
C
736 lines
25 KiB
C
/** @file
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Functions for accessing I2C registers.
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Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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--*/
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#include <Library/DebugLib.h>
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#include <Library/TimerLib.h>
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#include <PchRegs/PchRegsPcu.h>
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#include <PchRegs.h>
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#include <PlatformBaseAddresses.h>
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#include <PchRegs/PchRegsLpss.h>
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#include <Library/I2CLib.h>
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#include <Protocol/GlobalNvsArea.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <I2CRegs.h>
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#define GLOBAL_NVS_OFFSET(Field) (UINTN)((CHAR8*)&((EFI_GLOBAL_NVS_AREA*)0)->Field - (CHAR8*)0)
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#define PCIEX_BASE_ADDRESS 0xE0000000
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#define PCI_EXPRESS_BASE_ADDRESS ((VOID *) (UINTN) PCIEX_BASE_ADDRESS)
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#define MmPciAddress( Segment, Bus, Device, Function, Register ) \
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((UINTN)PCI_EXPRESS_BASE_ADDRESS + \
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(UINTN)(Bus << 20) + \
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(UINTN)(Device << 15) + \
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(UINTN)(Function << 12) + \
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(UINTN)(Register) \
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)
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#define PCI_D31F0_REG_BASE PCIEX_BASE_ADDRESS + (UINT32) (31 << 15)
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typedef struct _LPSS_PCI_DEVICE_INFO {
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UINTN Segment;
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UINTN BusNum;
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UINTN DeviceNum;
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UINTN FunctionNum;
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UINTN Bar0;
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UINTN Bar1;
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} LPSS_PCI_DEVICE_INFO;
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LPSS_PCI_DEVICE_INFO mLpssPciDeviceList[] = {
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{0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPSS_DMAC1, PCI_FUNCTION_NUMBER_PCH_LPSS_DMAC, 0xFE900000, 0xFE908000},
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{0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPSS_I2C, PCI_FUNCTION_NUMBER_PCH_LPSS_I2C0, 0xFE910000, 0xFE918000},
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{0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPSS_I2C, PCI_FUNCTION_NUMBER_PCH_LPSS_I2C1, 0xFE920000, 0xFE928000},
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{0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPSS_I2C, PCI_FUNCTION_NUMBER_PCH_LPSS_I2C2, 0xFE930000, 0xFE938000},
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{0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPSS_I2C, PCI_FUNCTION_NUMBER_PCH_LPSS_I2C3, 0xFE940000, 0xFE948000},
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{0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPSS_I2C, PCI_FUNCTION_NUMBER_PCH_LPSS_I2C4, 0xFE950000, 0xFE958000},
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{0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPSS_I2C, PCI_FUNCTION_NUMBER_PCH_LPSS_I2C5, 0xFE960000, 0xFE968000},
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{0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPSS_I2C, PCI_FUNCTION_NUMBER_PCH_LPSS_I2C6, 0xFE970000, 0xFE978000}
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};
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#define LPSS_PCI_DEVICE_NUMBER sizeof(mLpssPciDeviceList)/sizeof(LPSS_PCI_DEVICE_INFO)
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STATIC UINTN mI2CBaseAddress = 0;
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STATIC UINT16 mI2CSlaveAddress = 0;
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UINT16 mI2cMode=B_IC_RESTART_EN | B_IC_SLAVE_DISABLE | B_MASTER_MODE ;
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UINTN mI2cNvsBaseAddress[] = {
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GLOBAL_NVS_OFFSET(LDMA2Addr),
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GLOBAL_NVS_OFFSET(I2C1Addr),
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GLOBAL_NVS_OFFSET(I2C2Addr),
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GLOBAL_NVS_OFFSET(I2C3Addr),
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GLOBAL_NVS_OFFSET(I2C4Addr),
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GLOBAL_NVS_OFFSET(I2C5Addr),
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GLOBAL_NVS_OFFSET(I2C6Addr),
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GLOBAL_NVS_OFFSET(I2C7Addr)
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};
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/**
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This function get I2Cx controller base address (BAR0).
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@param I2cControllerIndex Bus Number of I2C controller.
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@return I2C BAR.
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**/
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UINTN
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GetI2cBarAddr(
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IN UINT8 I2cControllerIndex
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)
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{
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EFI_STATUS Status;
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EFI_GLOBAL_NVS_AREA_PROTOCOL *GlobalNvsArea;
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UINTN AcpiBaseAddr;
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UINTN PciMmBase=0;
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ASSERT(gBS!=NULL);
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Status = gBS->LocateProtocol (
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&gEfiGlobalNvsAreaProtocolGuid,
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NULL,
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&GlobalNvsArea
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);
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//
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// PCI mode from PEI ( Global NVS is not ready).
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//
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if (EFI_ERROR(Status)) {
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DEBUG ((EFI_D_INFO, "GetI2cBarAddr() gEfiGlobalNvsAreaProtocolGuid:%r\n", Status));
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//
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// Global NVS is not ready.
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//
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return 0;
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}
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AcpiBaseAddr = *(UINTN*)((CHAR8*)GlobalNvsArea->Area + mI2cNvsBaseAddress[I2cControllerIndex + 1]);
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//
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//PCI mode from DXE (global NVS protocal) to LPSS OnReadytoBoot(swith to ACPI).
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//
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if(AcpiBaseAddr==0) {
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PciMmBase = MmPciAddress (
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mLpssPciDeviceList[I2cControllerIndex + 1].Segment,
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mLpssPciDeviceList[I2cControllerIndex + 1].BusNum,
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mLpssPciDeviceList[I2cControllerIndex + 1].DeviceNum,
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mLpssPciDeviceList[I2cControllerIndex + 1].FunctionNum,
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0
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);
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DEBUG((EFI_D_ERROR, "\nGetI2cBarAddr() I2C Device %x %x %x PciMmBase:%x\n", \
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mLpssPciDeviceList[I2cControllerIndex + 1].BusNum, \
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mLpssPciDeviceList[I2cControllerIndex + 1].DeviceNum, \
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mLpssPciDeviceList[I2cControllerIndex + 1].FunctionNum, PciMmBase));
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if (MmioRead32 (PciMmBase) != 0xFFFFFFFF) {
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if((MmioRead32 (PciMmBase+R_PCH_LPSS_I2C_STSCMD)& B_PCH_LPSS_I2C_STSCMD_MSE)) {
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//
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// Get the address allocted.
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//
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mLpssPciDeviceList[I2cControllerIndex + 1].Bar0=MmioRead32 (PciMmBase+R_PCH_LPSS_I2C_BAR);
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mLpssPciDeviceList[I2cControllerIndex + 1].Bar1=MmioRead32 (PciMmBase+R_PCH_LPSS_I2C_BAR1);
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}
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}
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AcpiBaseAddr =mLpssPciDeviceList[I2cControllerIndex+1].Bar0;
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}
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//
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// ACPI mode from BDS: LPSS OnReadytoBoot
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//
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else {
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DEBUG ((EFI_D_INFO, "GetI2cBarAddr() NVS Varialable is updated by this LIB or LPSS \n"));
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}
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DEBUG ((EFI_D_INFO, "GetI2cBarAddr() I2cControllerIndex+1 0x%x AcpiBaseAddr:0x%x \n", (I2cControllerIndex + 1), AcpiBaseAddr));
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return AcpiBaseAddr;
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}
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/**
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This function enables I2C controllers.
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@param I2cControllerIndex Bus Number of I2C controllers.
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@return Result of the I2C initialization.
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**/
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EFI_STATUS
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ProgramPciLpssI2C (
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IN UINT8 I2cControllerIndex
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)
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{
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UINT32 PmcBase;
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UINTN PciMmBase=0;
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EFI_STATUS Status;
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EFI_GLOBAL_NVS_AREA_PROTOCOL *GlobalNvsArea;
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UINT32 PmcFunctionDsiable[]= {
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B_PCH_PMC_FUNC_DIS_LPSS2_FUNC1,
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B_PCH_PMC_FUNC_DIS_LPSS2_FUNC2,
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B_PCH_PMC_FUNC_DIS_LPSS2_FUNC3,
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B_PCH_PMC_FUNC_DIS_LPSS2_FUNC4,
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B_PCH_PMC_FUNC_DIS_LPSS2_FUNC5,
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B_PCH_PMC_FUNC_DIS_LPSS2_FUNC6,
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B_PCH_PMC_FUNC_DIS_LPSS2_FUNC7
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};
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DEBUG ((EFI_D_INFO, "ProgramPciLpssI2C() Start\n"));
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//
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// Set the VLV Function Disable Register to ZERO
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//
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PmcBase = MmioRead32 (PCI_D31F0_REG_BASE + R_PCH_LPC_PMC_BASE) & B_PCH_LPC_PMC_BASE_BAR;
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if(MmioRead32(PmcBase+R_PCH_PMC_FUNC_DIS)&PmcFunctionDsiable[I2cControllerIndex]) {
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DEBUG ((EFI_D_INFO, "ProgramPciLpssI2C() End:I2C[%x] is disabled\n",I2cControllerIndex));
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return EFI_NOT_READY;
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}
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DEBUG ((EFI_D_INFO, "ProgramPciLpssI2C()------------I2cControllerIndex=%x,PMC=%x\n",I2cControllerIndex,MmioRead32(PmcBase+R_PCH_PMC_FUNC_DIS)));
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{
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PciMmBase = MmPciAddress (
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mLpssPciDeviceList[I2cControllerIndex+1].Segment,
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mLpssPciDeviceList[I2cControllerIndex+1].BusNum,
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mLpssPciDeviceList[I2cControllerIndex+1].DeviceNum,
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mLpssPciDeviceList[I2cControllerIndex+1].FunctionNum,
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0
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);
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DEBUG((EFI_D_ERROR, "Program Pci Lpss I2C Device %x %x %x PciMmBase:%x\n", \
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mLpssPciDeviceList[I2cControllerIndex+1].BusNum, \
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mLpssPciDeviceList[I2cControllerIndex+1].DeviceNum, \
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mLpssPciDeviceList[I2cControllerIndex+1].FunctionNum, PciMmBase));
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if (MmioRead32 (PciMmBase) != 0xFFFFFFFF) {
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if((MmioRead32 (PciMmBase+R_PCH_LPSS_I2C_STSCMD)& B_PCH_LPSS_I2C_STSCMD_MSE)) {
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//
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// Get the address allocted.
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//
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mLpssPciDeviceList[I2cControllerIndex+1].Bar0=MmioRead32 (PciMmBase+R_PCH_LPSS_I2C_BAR);
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mLpssPciDeviceList[I2cControllerIndex+1].Bar1=MmioRead32 (PciMmBase+R_PCH_LPSS_I2C_BAR1);
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DEBUG((EFI_D_ERROR, "ProgramPciLpssI2C() bar0:0x%x bar1:0x%x\n",mLpssPciDeviceList[I2cControllerIndex+1].Bar0, mLpssPciDeviceList[I2cControllerIndex+1].Bar1));
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} else {
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//
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// Program BAR 0
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//
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ASSERT (((mLpssPciDeviceList[I2cControllerIndex+1].Bar0 & B_PCH_LPSS_I2C_BAR_BA) == mLpssPciDeviceList[I2cControllerIndex+1].Bar0) && (mLpssPciDeviceList[I2cControllerIndex+1].Bar0 != 0));
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MmioWrite32 ((UINTN) (PciMmBase + R_PCH_LPSS_I2C_BAR), (UINT32) (mLpssPciDeviceList[I2cControllerIndex+1].Bar0 & B_PCH_LPSS_I2C_BAR_BA));
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//
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// Program BAR 1
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//
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ASSERT (((mLpssPciDeviceList[I2cControllerIndex+1].Bar1 & B_PCH_LPSS_I2C_BAR1_BA) == mLpssPciDeviceList[I2cControllerIndex+1].Bar1) && (mLpssPciDeviceList[I2cControllerIndex+1].Bar1 != 0));
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MmioWrite32 ((UINTN) (PciMmBase + R_PCH_LPSS_I2C_BAR1), (UINT32) (mLpssPciDeviceList[I2cControllerIndex+1].Bar1 & B_PCH_LPSS_I2C_BAR1_BA));
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//
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// Bus Master Enable & Memory Space Enable
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//
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MmioOr32 ((UINTN) (PciMmBase + R_PCH_LPSS_I2C_STSCMD), (UINT32) (B_PCH_LPSS_I2C_STSCMD_BME | B_PCH_LPSS_I2C_STSCMD_MSE));
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ASSERT (MmioRead32 (mLpssPciDeviceList[I2cControllerIndex+1].Bar0) != 0xFFFFFFFF);
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}
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//
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// Release Resets
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//
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MmioWrite32 (mLpssPciDeviceList[I2cControllerIndex+1].Bar0 + R_PCH_LPIO_I2C_MEM_RESETS,(B_PCH_LPIO_I2C_MEM_RESETS_FUNC | B_PCH_LPIO_I2C_MEM_RESETS_APB));
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//
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// Activate Clocks
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//
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MmioWrite32 (mLpssPciDeviceList[I2cControllerIndex+1].Bar0 + R_PCH_LPSS_I2C_MEM_PCP,0x80020003);//No use for A0
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DEBUG ((EFI_D_INFO, "ProgramPciLpssI2C() Programmed()\n"));
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}
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//
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// BDS: already switched to ACPI mode
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//
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else {
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ASSERT(gBS!=NULL);
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Status = gBS->LocateProtocol (
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&gEfiGlobalNvsAreaProtocolGuid,
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NULL,
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&GlobalNvsArea
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);
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if (EFI_ERROR(Status)) {
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DEBUG ((EFI_D_INFO, "GetI2cBarAddr() gEfiGlobalNvsAreaProtocolGuid:%r\n", Status));
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//
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// gEfiGlobalNvsAreaProtocolGuid is not ready.
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//
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return 0;
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}
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mLpssPciDeviceList[I2cControllerIndex + 1].Bar0 = *(UINTN*)((CHAR8*)GlobalNvsArea->Area + mI2cNvsBaseAddress[I2cControllerIndex + 1]);
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DEBUG ((EFI_D_INFO, "ProgramPciLpssI2C(): is switched to ACPI 0x:%x \n",mLpssPciDeviceList[I2cControllerIndex + 1].Bar0));
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}
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}
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DEBUG ((EFI_D_INFO, "ProgramPciLpssI2C() End\n"));
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return EFI_SUCCESS;
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}
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/**
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Disable I2C Bus.
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@param VOID.
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@return Result of the I2C disabling.
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**/
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RETURN_STATUS
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I2cDisable (
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VOID
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)
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{
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//
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// 0.1 seconds
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//
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UINT32 NumTries = 10000;
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MmioWrite32 ( mI2CBaseAddress + R_IC_ENABLE, 0 );
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while ( 0 != ( MmioRead32 ( mI2CBaseAddress + R_IC_ENABLE_STATUS) & 1)) {
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MicroSecondDelay (10);
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NumTries --;
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if(0 == NumTries) {
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return RETURN_NOT_READY;
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}
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}
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return RETURN_SUCCESS;
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}
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/**
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Enable I2C Bus.
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@param VOID.
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@return Result of the I2C disabling.
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**/
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RETURN_STATUS
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I2cEnable (
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VOID
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)
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{
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//
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// 0.1 seconds
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//
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UINT32 NumTries = 10000;
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MmioWrite32 (mI2CBaseAddress + R_IC_ENABLE, 1);
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while (0 == (MmioRead32 (mI2CBaseAddress + R_IC_ENABLE_STATUS) & 1)) {
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MicroSecondDelay (10);
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NumTries --;
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if(0 == NumTries){
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return RETURN_NOT_READY;
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}
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}
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return RETURN_SUCCESS;
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}
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/**
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Enable I2C Bus.
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@param VOID.
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@return Result of the I2C enabling.
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**/
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RETURN_STATUS
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I2cBusFrequencySet (
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IN UINTN BusClockHertz
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)
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{
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DEBUG((EFI_D_INFO,"InputFreq BusClockHertz: %d\r\n",BusClockHertz));
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//
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// Set the 100 KHz clock divider according to SV result and I2C spec
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//
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MmioWrite32 ( mI2CBaseAddress + R_IC_SS_SCL_HCNT, (UINT16)0x214 );
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MmioWrite32 ( mI2CBaseAddress + R_IC_SS_SCL_LCNT, (UINT16)0x272 );
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//
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// Set the 400 KHz clock divider according to SV result and I2C spec
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//
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MmioWrite32 ( mI2CBaseAddress + R_IC_FS_SCL_HCNT, (UINT16)0x50 );
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MmioWrite32 ( mI2CBaseAddress + R_IC_FS_SCL_LCNT, (UINT16)0xAD );
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switch ( BusClockHertz ) {
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case 100 * 1000:
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MmioWrite32 ( mI2CBaseAddress + R_IC_SDA_HOLD, (UINT16)0x40);//100K
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mI2cMode = V_SPEED_STANDARD;
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break;
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case 400 * 1000:
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MmioWrite32 ( mI2CBaseAddress + R_IC_SDA_HOLD, (UINT16)0x32);//400K
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mI2cMode = V_SPEED_FAST;
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break;
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default:
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MmioWrite32 ( mI2CBaseAddress + R_IC_SDA_HOLD, (UINT16)0x09);//3.4M
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mI2cMode = V_SPEED_HIGH;
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}
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//
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// Select the frequency counter,
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// Enable restart condition,
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// Enable master FSM, disable slave FSM.
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//
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mI2cMode |= B_IC_RESTART_EN | B_IC_SLAVE_DISABLE | B_MASTER_MODE;
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return EFI_SUCCESS;
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}
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|
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/**
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Initializes the host controller to execute I2C commands.
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|
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@param I2cControllerIndex Index of I2C controller in LPSS device. 0 represents I2C0, which is PCI function 1 of LPSS device.
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@return EFI_SUCCESS Opcode initialization on the I2C host controller completed.
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@return EFI_DEVICE_ERROR Device error, operation failed.
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**/
|
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EFI_STATUS
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I2CInit (
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IN UINT8 I2cControllerIndex,
|
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IN UINT16 SlaveAddress
|
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)
|
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{
|
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EFI_STATUS Status=RETURN_SUCCESS;
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UINT32 NumTries = 0;
|
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UINTN GnvsI2cBarAddr=0;
|
|
|
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//
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// Verify the parameters
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//
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if ((1023 < SlaveAddress) || (6 < I2cControllerIndex)) {
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Status = RETURN_INVALID_PARAMETER;
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DEBUG((EFI_D_INFO,"I2CInit Exit with RETURN_INVALID_PARAMETER\r\n"));
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return Status;
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}
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MmioWrite32 ( mI2CBaseAddress + R_IC_TAR, (UINT16)SlaveAddress );
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mI2CSlaveAddress = SlaveAddress;
|
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|
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//
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// 1.PEI: program and init ( before pci enumeration).
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// 2.DXE:update address and re-init ( after pci enumeration).
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// 3.BDS:update ACPI address and re-init ( after acpi mode is enabled).
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//
|
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if(mI2CBaseAddress == mLpssPciDeviceList[I2cControllerIndex + 1].Bar0) {
|
|
|
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//
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// I2CInit is already called.
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//
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GnvsI2cBarAddr=GetI2cBarAddr(I2cControllerIndex);
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|
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if((GnvsI2cBarAddr == 0)||(GnvsI2cBarAddr == mI2CBaseAddress)) {
|
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DEBUG((EFI_D_INFO,"I2CInit Exit with mI2CBaseAddress:%x == [%x].Bar0\r\n",mI2CBaseAddress,I2cControllerIndex+1));
|
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return RETURN_SUCCESS;
|
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}
|
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}
|
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|
|
Status=ProgramPciLpssI2C(I2cControllerIndex);
|
|
if(Status!=EFI_SUCCESS) {
|
|
return Status;
|
|
}
|
|
|
|
|
|
mI2CBaseAddress = (UINT32) mLpssPciDeviceList[I2cControllerIndex + 1].Bar0;
|
|
DEBUG ((EFI_D_ERROR, "mI2CBaseAddress = 0x%x \n",mI2CBaseAddress));
|
|
|
|
//
|
|
// 1 seconds.
|
|
//
|
|
NumTries = 10000;
|
|
while ((1 == ( MmioRead32 ( mI2CBaseAddress + R_IC_STATUS) & STAT_MST_ACTIVITY ))) {
|
|
MicroSecondDelay(10);
|
|
NumTries --;
|
|
if(0 == NumTries) {
|
|
DEBUG((EFI_D_INFO, "Try timeout\r\n"));
|
|
return RETURN_DEVICE_ERROR;
|
|
}
|
|
}
|
|
|
|
Status = I2cDisable();
|
|
DEBUG((EFI_D_INFO, "I2cDisable Status = %r\r\n", Status));
|
|
I2cBusFrequencySet(400 * 1000);
|
|
|
|
MmioWrite32(mI2CBaseAddress + R_IC_INTR_MASK, 0x0);
|
|
if (0x7f < SlaveAddress )
|
|
SlaveAddress = ( SlaveAddress & 0x3ff ) | IC_TAR_10BITADDR_MASTER;
|
|
MmioWrite32 ( mI2CBaseAddress + R_IC_TAR, (UINT16)SlaveAddress );
|
|
MmioWrite32 ( mI2CBaseAddress + R_IC_RX_TL, 0);
|
|
MmioWrite32 ( mI2CBaseAddress + R_IC_TX_TL, 0 );
|
|
MmioWrite32 ( mI2CBaseAddress + R_IC_CON, mI2cMode);
|
|
Status = I2cEnable();
|
|
|
|
DEBUG((EFI_D_INFO, "I2cEnable Status = %r\r\n", Status));
|
|
MmioRead32 ( mI2CBaseAddress + R_IC_CLR_TX_ABRT );
|
|
|
|
return EFI_SUCCESS;
|
|
}
|
|
|
|
/**
|
|
Reads a Byte from I2C Device.
|
|
|
|
@param I2cControllerIndex I2C Bus no to which the I2C device has been connected
|
|
@param SlaveAddress Device Address from which the byte value has to be read
|
|
@param Offset Offset from which the data has to be read
|
|
@param *Byte Address to which the value read has to be stored
|
|
@param Start Whether a RESTART is issued before the byte is sent or received
|
|
@param End Whether STOP is generated after a data byte is sent or received
|
|
|
|
@return EFI_SUCCESS IF the byte value has been successfully read
|
|
@return EFI_DEVICE_ERROR Operation Failed, Device Error
|
|
**/
|
|
EFI_STATUS
|
|
ByteReadI2CBasic(
|
|
IN UINT8 I2cControllerIndex,
|
|
IN UINT8 SlaveAddress,
|
|
IN UINTN ReadBytes,
|
|
OUT UINT8 *ReadBuffer,
|
|
IN UINT8 Start,
|
|
IN UINT8 End
|
|
)
|
|
{
|
|
|
|
EFI_STATUS Status;
|
|
UINT32 I2cStatus;
|
|
UINT16 ReceiveData;
|
|
UINT8 *ReceiveDataEnd;
|
|
UINT8 *ReceiveRequest;
|
|
UINT16 RawIntrStat;
|
|
UINT32 Count=0;
|
|
|
|
Status = EFI_SUCCESS;
|
|
|
|
ReceiveDataEnd = &ReadBuffer [ReadBytes];
|
|
if( ReadBytes ) {
|
|
|
|
ReceiveRequest = ReadBuffer;
|
|
DEBUG((EFI_D_INFO,"Read: ---------------%d bytes to RX\r\n",ReceiveDataEnd - ReceiveRequest));
|
|
|
|
while ((ReceiveDataEnd > ReceiveRequest) || (ReceiveDataEnd > ReadBuffer)) {
|
|
|
|
//
|
|
// Check for NACK
|
|
//
|
|
RawIntrStat = (UINT16)MmioRead32 (mI2CBaseAddress + R_IC_RawIntrStat);
|
|
if ( 0 != ( RawIntrStat & I2C_INTR_TX_ABRT )) {
|
|
MmioRead32 ( mI2CBaseAddress + R_IC_CLR_TX_ABRT );
|
|
Status = RETURN_DEVICE_ERROR;
|
|
DEBUG((EFI_D_INFO,"TX ABRT ,%d bytes hasn't been transferred\r\n",ReceiveDataEnd - ReceiveRequest));
|
|
break;
|
|
}
|
|
|
|
//
|
|
// Determine if another byte was received
|
|
//
|
|
I2cStatus = (UINT16)MmioRead32 (mI2CBaseAddress + R_IC_STATUS);
|
|
if (0 != ( I2cStatus & STAT_RFNE )) {
|
|
ReceiveData = (UINT16)MmioRead32 ( mI2CBaseAddress + R_IC_DATA_CMD );
|
|
*ReadBuffer++ = (UINT8)ReceiveData;
|
|
DEBUG((EFI_D_INFO,"MmioRead32 ,1 byte 0x:%x is received\r\n",ReceiveData));
|
|
}
|
|
|
|
if(ReceiveDataEnd == ReceiveRequest) {
|
|
MicroSecondDelay ( FIFO_WRITE_DELAY );
|
|
DEBUG((EFI_D_INFO,"ReceiveDataEnd==ReceiveRequest------------%x\r\n",I2cStatus & STAT_RFNE));
|
|
Count++;
|
|
if(Count<1024) {
|
|
//
|
|
// To avoid sys hung without ul-pmc device on RVP,
|
|
// waiting the last request to get data and make (ReceiveDataEnd > ReadBuffer) =TRUE.
|
|
//
|
|
continue;
|
|
} else {
|
|
break;
|
|
}
|
|
}
|
|
|
|
//
|
|
// Wait until a read request will fit.
|
|
//
|
|
if (0 == (I2cStatus & STAT_TFNF)) {
|
|
DEBUG((EFI_D_INFO,"Wait until a read request will fit\r\n"));
|
|
MicroSecondDelay (10);
|
|
continue;
|
|
}
|
|
|
|
//
|
|
// Issue the next read request.
|
|
//
|
|
if(End && Start) {
|
|
MmioWrite32 ( mI2CBaseAddress + R_IC_DATA_CMD, B_READ_CMD|B_CMD_RESTART|B_CMD_STOP);
|
|
} else if (!End && Start) {
|
|
MmioWrite32 ( mI2CBaseAddress + R_IC_DATA_CMD, B_READ_CMD|B_CMD_RESTART);
|
|
} else if (End && !Start) {
|
|
MmioWrite32 ( mI2CBaseAddress + R_IC_DATA_CMD, B_READ_CMD|B_CMD_STOP);
|
|
} else if (!End && !Start) {
|
|
MmioWrite32 ( mI2CBaseAddress + R_IC_DATA_CMD, B_READ_CMD);
|
|
}
|
|
MicroSecondDelay (FIFO_WRITE_DELAY);
|
|
|
|
ReceiveRequest += 1;
|
|
}
|
|
}
|
|
|
|
return Status;
|
|
}
|
|
|
|
/**
|
|
Writes a Byte to I2C Device.
|
|
|
|
@param I2cControllerIndex I2C Bus no to which the I2C device has been connected
|
|
@param SlaveAddress Device Address from which the byte value has to be written
|
|
@param Offset Offset from which the data has to be read
|
|
@param *Byte Address to which the value written is stored
|
|
@param Start Whether a RESTART is issued before the byte is sent or received
|
|
@param End Whether STOP is generated after a data byte is sent or received
|
|
|
|
@return EFI_SUCCESS IF the byte value has been successfully written
|
|
@return EFI_DEVICE_ERROR Operation Failed, Device Error
|
|
**/
|
|
EFI_STATUS ByteWriteI2CBasic(
|
|
IN UINT8 I2cControllerIndex,
|
|
IN UINT8 SlaveAddress,
|
|
IN UINTN WriteBytes,
|
|
IN UINT8 *WriteBuffer,
|
|
IN UINT8 Start,
|
|
IN UINT8 End
|
|
)
|
|
{
|
|
|
|
EFI_STATUS Status;
|
|
UINT32 I2cStatus;
|
|
UINT8 *TransmitEnd;
|
|
UINT16 RawIntrStat;
|
|
UINT32 Count=0;
|
|
|
|
Status = EFI_SUCCESS;
|
|
|
|
Status=I2CInit(I2cControllerIndex, SlaveAddress);
|
|
if(Status!=EFI_SUCCESS)
|
|
return Status;
|
|
|
|
TransmitEnd = &WriteBuffer[WriteBytes];
|
|
if( WriteBytes ) {
|
|
DEBUG((EFI_D_INFO,"Write: --------------%d bytes to TX\r\n",TransmitEnd - WriteBuffer));
|
|
while (TransmitEnd > WriteBuffer) {
|
|
I2cStatus = MmioRead32 (mI2CBaseAddress + R_IC_STATUS);
|
|
RawIntrStat = (UINT16)MmioRead32 (mI2CBaseAddress + R_IC_RawIntrStat);
|
|
if (0 != ( RawIntrStat & I2C_INTR_TX_ABRT)) {
|
|
MmioRead32 ( mI2CBaseAddress + R_IC_CLR_TX_ABRT);
|
|
Status = RETURN_DEVICE_ERROR;
|
|
DEBUG((EFI_D_ERROR,"TX ABRT TransmitEnd:0x%x WriteBuffer:0x%x\r\n", TransmitEnd, WriteBuffer));
|
|
break;
|
|
}
|
|
if (0 == (I2cStatus & STAT_TFNF)) {
|
|
//
|
|
// If TX not full , will send cmd or continue to wait
|
|
//
|
|
MicroSecondDelay (FIFO_WRITE_DELAY);
|
|
continue;
|
|
}
|
|
|
|
if(End && Start) {
|
|
MmioWrite32 (mI2CBaseAddress + R_IC_DATA_CMD, (*WriteBuffer++)|B_CMD_RESTART|B_CMD_STOP);
|
|
} else if (!End && Start) {
|
|
MmioWrite32 (mI2CBaseAddress + R_IC_DATA_CMD, (*WriteBuffer++)|B_CMD_RESTART);
|
|
} else if (End && !Start) {
|
|
MmioWrite32 (mI2CBaseAddress + R_IC_DATA_CMD, (*WriteBuffer++)|B_CMD_STOP);
|
|
} else if (!End && !Start ) {
|
|
MmioWrite32 (mI2CBaseAddress + R_IC_DATA_CMD, (*WriteBuffer++));
|
|
}
|
|
|
|
//
|
|
// Add a small delay to work around some odd behavior being seen. Without this delay bytes get dropped.
|
|
//
|
|
MicroSecondDelay ( FIFO_WRITE_DELAY );//wait after send cmd
|
|
|
|
//
|
|
// Time out
|
|
//
|
|
while(1) {
|
|
RawIntrStat = MmioRead16 ( mI2CBaseAddress + R_IC_RawIntrStat );
|
|
if (0 != ( RawIntrStat & I2C_INTR_TX_ABRT)) {
|
|
MmioRead16 (mI2CBaseAddress + R_IC_CLR_TX_ABRT);
|
|
Status = RETURN_DEVICE_ERROR;
|
|
DEBUG((EFI_D_ERROR,"TX ABRT TransmitEnd:0x%x WriteBuffer:0x%x\r\n", TransmitEnd, WriteBuffer));
|
|
}
|
|
if(0 == MmioRead16(mI2CBaseAddress + R_IC_TXFLR)) break;
|
|
|
|
MicroSecondDelay (FIFO_WRITE_DELAY);
|
|
Count++;
|
|
if(Count<1024) {
|
|
//
|
|
// to avoid sys hung without ul-pmc device on RVP.
|
|
// Waiting the last request to get data and make (ReceiveDataEnd > ReadBuffer) =TRUE.
|
|
//
|
|
continue;
|
|
} else {
|
|
break;
|
|
}
|
|
}//while( 1 )
|
|
}
|
|
|
|
}
|
|
|
|
return Status;
|
|
}
|
|
|
|
/**
|
|
Reads a Byte from I2C Device.
|
|
|
|
@param I2cControllerIndex I2C Bus no to which the I2C device has been connected
|
|
@param SlaveAddress Device Address from which the byte value has to be read
|
|
@param Offset Offset from which the data has to be read
|
|
@param ReadBytes Number of bytes to be read
|
|
@param *ReadBuffer Address to which the value read has to be stored
|
|
|
|
@return EFI_SUCCESS IF the byte value has been successfully read
|
|
@return EFI_DEVICE_ERROR Operation Failed, Device Error
|
|
**/
|
|
EFI_STATUS ByteReadI2C(
|
|
IN UINT8 I2cControllerIndex,
|
|
IN UINT8 SlaveAddress,
|
|
IN UINT8 Offset,
|
|
IN UINTN ReadBytes,
|
|
OUT UINT8 *ReadBuffer
|
|
)
|
|
{
|
|
EFI_STATUS Status;
|
|
|
|
DEBUG ((EFI_D_INFO, "ByteReadI2C:---offset:0x%x\n",Offset));
|
|
Status = ByteWriteI2CBasic(I2cControllerIndex, SlaveAddress,1,&Offset,TRUE,FALSE);
|
|
Status = ByteReadI2CBasic(I2cControllerIndex, SlaveAddress,ReadBytes,ReadBuffer,TRUE,TRUE);
|
|
|
|
return Status;
|
|
}
|
|
|
|
/**
|
|
Writes a Byte to I2C Device.
|
|
|
|
@param I2cControllerIndex I2C Bus no to which the I2C device has been connected
|
|
@param SlaveAddress Device Address from which the byte value has to be written
|
|
@param Offset Offset from which the data has to be written
|
|
@param WriteBytes Number of bytes to be written
|
|
@param *Byte Address to which the value written is stored
|
|
|
|
@return EFI_SUCCESS IF the byte value has been successfully read
|
|
@return EFI_DEVICE_ERROR Operation Failed, Device Error
|
|
**/
|
|
EFI_STATUS ByteWriteI2C(
|
|
IN UINT8 I2cControllerIndex,
|
|
IN UINT8 SlaveAddress,
|
|
IN UINT8 Offset,
|
|
IN UINTN WriteBytes,
|
|
IN UINT8 *WriteBuffer
|
|
)
|
|
{
|
|
EFI_STATUS Status;
|
|
|
|
DEBUG ((EFI_D_INFO, "ByteWriteI2C:---offset/bytes/buf:0x%x,0x%x,0x%x,0x%x\n",Offset,WriteBytes,WriteBuffer,*WriteBuffer));
|
|
Status = ByteWriteI2CBasic(I2cControllerIndex, SlaveAddress,1,&Offset,TRUE,FALSE);
|
|
Status = ByteWriteI2CBasic(I2cControllerIndex, SlaveAddress,WriteBytes,WriteBuffer,FALSE,TRUE);
|
|
|
|
return Status;
|
|
}
|