mirror of https://github.com/acidanthera/audk.git
193 lines
5.9 KiB
C
193 lines
5.9 KiB
C
/** @file
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This PEIM will parse the hoblist from fsp and report them into pei core.
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This file contains the main entrypoint of the PEIM.
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Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <PiPei.h>
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#include <Library/IoLib.h>
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#include <Library/SerialPortLib.h>
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#define PCI_IDX 0xCF8
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#define PCI_DAT 0xCFC
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#define PCI_LPC_BASE (0x8000F800)
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#define PCI_LPC_REG(x) (PCI_LPC_BASE + (x))
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#define PMC_BASE_ADDRESS 0xFED03000 // PMC Memory Base Address
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#define R_PCH_LPC_PMC_BASE 0x44 // PBASE, 32bit, 512 Bytes
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#define B_PCH_LPC_PMC_BASE_EN BIT1 // Enable Bit
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#define R_PCH_PMC_GEN_PMCON_1 0x20 // General PM Configuration 1
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#define B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR BIT14 // SUS Well Power Failure
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#define B_PCH_PMC_GEN_PMCON_PWROK_FLR BIT16 // PWROK Failure
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#define R_PCH_LPC_UART_CTRL 0x80 // UART Control
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#define B_PCH_LPC_UART_CTRL_COM1_EN BIT0 // COM1 Enable
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#define ILB_BASE_ADDRESS 0xFED08000 // ILB Memory Base Address
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#define R_PCH_ILB_IRQE 0x88 // IRQ Enable Control
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#define IO_BASE_ADDRESS 0xFED0C000 // IO Memory Base Address
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#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ3 BIT3 // UART IRQ3 Enable
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#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ4 BIT4 // UART IRQ4 Enable
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#define PCIEX_BASE_ADDRESS 0xE0000000
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#define PCI_EXPRESS_BASE_ADDRESS PCIEX_BASE_ADDRESS
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#define PciD31F0RegBase PCIEX_BASE_ADDRESS + (UINT32) (31 << 15)
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#define SB_RCBA 0xfed1c000
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typedef enum {
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PchA0 = 0,
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PchA1 = 1,
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PchB0 = 2,
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PchB1 = 3,
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PchB2 = 4,
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PchB3 = 5,
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PchC0 = 6,
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PchSteppingMax
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} PCH_STEPPING;
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#define MmPciAddress( Segment, Bus, Device, Function, Register ) \
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( (UINTN)PCI_EXPRESS_BASE_ADDRESS + \
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(UINTN)(Bus << 20) + \
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(UINTN)(Device << 15) + \
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(UINTN)(Function << 12) + \
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(UINTN)(Register) \
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)
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#define DEFAULT_PCI_BUS_NUMBER_PCH 0
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#define PCI_DEVICE_NUMBER_PCH_LPC 31
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#define PCI_FUNCTION_NUMBER_PCH_LPC 0
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#define R_PCH_LPC_RID_CC 0x08 // Revision ID & Class Code
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#define V_PCH_LPC_RID_0 0x01 // A0 Stepping (17 x 17)
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#define V_PCH_LPC_RID_1 0x02 // A0 Stepping (25 x 27)
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#define V_PCH_LPC_RID_2 0x03 // A1 Stepping (17 x 17)
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#define V_PCH_LPC_RID_3 0x04 // A1 Stepping (25 x 27)
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#define V_PCH_LPC_RID_4 0x05 // B0 Stepping (17 x 17)
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#define V_PCH_LPC_RID_5 0x06 // B0 Stepping (25 x 27)
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#define V_PCH_LPC_RID_6 0x07 // B1 Stepping (17 x 17)
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#define V_PCH_LPC_RID_7 0x08 // B1 Stepping (25 x 27)
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#define V_PCH_LPC_RID_8 0x09 // B2 Stepping (17 x 17)
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#define V_PCH_LPC_RID_9 0x0A // B2 Stepping (25 x 27)
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#define V_PCH_LPC_RID_A 0x0B // B3 Stepping (17 x 17)
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#define V_PCH_LPC_RID_B 0x0C // B3 Stepping (25 x 27)
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#define V_PCH_LPC_RID_C 0x0D // C0 Stepping (17 x 17)
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#define V_PCH_LPC_RID_D 0x0E // C0 Stepping (25 x 27)
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/**
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Return Pch stepping type
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@param[in] None
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@retval PCH_STEPPING Pch stepping type
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**/
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PCH_STEPPING
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EFIAPI
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PchStepping (
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VOID
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)
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{
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UINT8 RevId;
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RevId = MmioRead8 (
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MmPciAddress (0,
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_LPC,
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PCI_FUNCTION_NUMBER_PCH_LPC,
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R_PCH_LPC_RID_CC)
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);
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switch (RevId) {
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case V_PCH_LPC_RID_0:
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case V_PCH_LPC_RID_1:
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return PchA0;
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break;
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case V_PCH_LPC_RID_2:
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case V_PCH_LPC_RID_3:
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return PchA1;
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break;
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case V_PCH_LPC_RID_4:
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case V_PCH_LPC_RID_5:
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return PchB0;
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break;
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case V_PCH_LPC_RID_6:
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case V_PCH_LPC_RID_7:
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return PchB1;
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break;
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case V_PCH_LPC_RID_8:
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case V_PCH_LPC_RID_9:
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return PchB2;
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break;
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case V_PCH_LPC_RID_A:
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case V_PCH_LPC_RID_B:
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return PchB3;
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break;
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case V_PCH_LPC_RID_C:
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case V_PCH_LPC_RID_D:
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return PchC0;
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break;
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default:
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return PchSteppingMax;
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break;
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}
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}
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/**
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Enable legacy decoding on ICH6
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@param[in] none
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@retval EFI_SUCCESS Always returns success.
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**/
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VOID
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EnableInternalUart(
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VOID
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)
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{
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//
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// Program and enable PMC Base.
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//
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IoWrite32 (PCI_IDX, PCI_LPC_REG(R_PCH_LPC_PMC_BASE));
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IoWrite32 (PCI_DAT, (PMC_BASE_ADDRESS | B_PCH_LPC_PMC_BASE_EN));
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//
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// Enable COM1 for debug message output.
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//
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MmioAndThenOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, (UINT32) (~(B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR + B_PCH_PMC_GEN_PMCON_PWROK_FLR)), BIT24);
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//
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// Silicon Steppings
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//
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if (PchStepping()>= PchB0)
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MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8) V_PCH_ILB_IRQE_UARTIRQEN_IRQ4);
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else
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MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8) V_PCH_ILB_IRQE_UARTIRQEN_IRQ3);
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MmioAnd32(IO_BASE_ADDRESS + 0x0520, (UINT32)~(0x00000187));
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MmioOr32 (IO_BASE_ADDRESS + 0x0520, (UINT32)0x81); // UART3_RXD-L
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MmioAnd32(IO_BASE_ADDRESS + 0x0530, (UINT32)~(0x00000007));
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MmioOr32 (IO_BASE_ADDRESS + 0x0530, (UINT32)0x1); // UART3_RXD-L
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MmioOr8 (PciD31F0RegBase + R_PCH_LPC_UART_CTRL, (UINT8) B_PCH_LPC_UART_CTRL_COM1_EN);
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SerialPortInitialize ();
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SerialPortWrite ((UINT8 *)"EnableInternalUart!\r\n", sizeof("EnableInternalUart!\r\n") - 1);
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return ;
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}
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