mirror of https://github.com/acidanthera/audk.git
241 lines
8.4 KiB
C
241 lines
8.4 KiB
C
/** @file
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Framework PEIM to initialize memory on an DDR2 SDRAM Memory Controller.
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Copyright (c) 2013 - 2016 Intel Corporation.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _MRC_WRAPPER_H
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#define _MRC_WRAPPER_H
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#include <Ppi/QNCMemoryInit.h>
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#include "PlatformEarlyInit.h"
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//
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// Define the default memory areas required
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//
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#define EDKII_RESERVED_SIZE_PAGES 0x20
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#define ACPI_NVS_SIZE_PAGES 0x60
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#define RUNTIME_SERVICES_DATA_SIZE_PAGES 0x20
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#define RUNTIME_SERVICES_CODE_SIZE_PAGES 0x80
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#define ACPI_RECLAIM_SIZE_PAGES 0x20
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#define EDKII_DXE_MEM_SIZE_PAGES 0x20
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#define AP_STARTUP_VECTOR 0x00097000
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//
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// Maximum number of "Socket Sets", where a "Socket Set is a set of matching
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// DIMM's from the various channels
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//
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#define MAX_SOCKET_SETS 2
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//
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// Maximum number of memory ranges supported by the memory controller
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//
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#define MAX_RANGES (MAX_ROWS + 5)
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//
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// Min. of 48MB PEI phase
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//
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#define PEI_MIN_MEMORY_SIZE (6 * 0x800000)
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#define PEI_RECOVERY_MIN_MEMORY_SIZE (6 * 0x800000)
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#define PEI_MEMORY_RANGE_OPTION_ROM UINT32
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#define PEI_MR_OPTION_ROM_NONE 0x00000000
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//
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// SMRAM Memory Range
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//
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#define PEI_MEMORY_RANGE_SMRAM UINT32
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#define PEI_MR_SMRAM_ALL 0xFFFFFFFF
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#define PEI_MR_SMRAM_NONE 0x00000000
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#define PEI_MR_SMRAM_CACHEABLE_MASK 0x80000000
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#define PEI_MR_SMRAM_SEGTYPE_MASK 0x00FF0000
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#define PEI_MR_SMRAM_ABSEG_MASK 0x00010000
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#define PEI_MR_SMRAM_HSEG_MASK 0x00020000
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#define PEI_MR_SMRAM_TSEG_MASK 0x00040000
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//
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// SMRAM Size is a multiple of 128KB.
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//
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#define PEI_MR_SMRAM_SIZE_MASK 0x0000FFFF
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//
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// Pci Memory Hole
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//
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#define PEI_MEMORY_RANGE_PCI_MEMORY UINT32
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typedef enum {
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Ignore,
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Quick,
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Sparse,
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Extensive
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} PEI_MEMORY_TEST_OP;
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//
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// MRC Params Variable structure.
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//
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typedef struct {
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MrcTimings_t timings; // Actual MRC config values saved in variable store.
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UINT8 VariableStorePad[8]; // Allow for data stored in variable is required to be multiple of 8bytes.
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} PLATFORM_VARIABLE_MEMORY_CONFIG_DATA;
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///
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/// MRC Params Platform Data Flags bits
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///
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#define PDAT_MRC_FLAG_ECC_EN BIT0
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#define PDAT_MRC_FLAG_SCRAMBLE_EN BIT1
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#define PDAT_MRC_FLAG_MEMTEST_EN BIT2
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#define PDAT_MRC_FLAG_TOP_TREE_EN BIT3 ///< 0b DDR "fly-by" topology else 1b DDR "tree" topology.
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#define PDAT_MRC_FLAG_WR_ODT_EN BIT4 ///< If set ODR signal is asserted to DRAM devices on writes.
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///
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/// MRC Params Platform Data.
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///
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typedef struct {
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UINT32 Flags; ///< Bitmap of PDAT_MRC_FLAG_XXX defs above.
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UINT8 DramWidth; ///< 0=x8, 1=x16, others=RESERVED.
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UINT8 DramSpeed; ///< 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU support 1066 memory.
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UINT8 DramType; ///< 0=DDR3,1=DDR3L, others=RESERVED.
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UINT8 RankMask; ///< bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED.
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UINT8 ChanMask; ///< bit[0] CHAN0_EN, others=RESERVED.
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UINT8 ChanWidth; ///< 1=x16, others=RESERVED.
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UINT8 AddrMode; ///< 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED.
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UINT8 SrInt; ///< 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE.
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UINT8 SrTemp; ///< 0=normal, 1=extended, others=RESERVED.
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UINT8 DramRonVal; ///< 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver impedance control.
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UINT8 DramRttNomVal; ///< 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED.
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UINT8 DramRttWrVal; ///< 0=off others=RESERVED.
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UINT8 SocRdOdtVal; ///< 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED.
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UINT8 SocWrRonVal; ///< 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED.
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UINT8 SocWrSlewRate; ///< 0=2.5V/ns, 1=4V/ns, others=RESERVED.
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UINT8 DramDensity; ///< 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED.
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UINT32 tRAS; ///< ACT to PRE command period in picoseconds.
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UINT32 tWTR; ///< Delay from start of internal write transaction to internal read command in picoseconds.
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UINT32 tRRD; ///< ACT to ACT command period (JESD79 specific to page size 1K/2K) in picoseconds.
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UINT32 tFAW; ///< Four activate window (JESD79 specific to page size 1K/2K) in picoseconds.
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UINT8 tCL; ///< DRAM CAS Latency in clocks.
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} PDAT_MRC_ITEM;
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//
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// Memory range types
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//
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typedef enum {
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DualChannelDdrMainMemory,
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DualChannelDdrSmramCacheable,
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DualChannelDdrSmramNonCacheable,
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DualChannelDdrGraphicsMemoryCacheable,
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DualChannelDdrGraphicsMemoryNonCacheable,
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DualChannelDdrReservedMemory,
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DualChannelDdrMaxMemoryRangeType
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} PEI_DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE;
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//
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// Memory map range information
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//
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typedef struct {
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EFI_PHYSICAL_ADDRESS PhysicalAddress;
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EFI_PHYSICAL_ADDRESS CpuAddress;
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EFI_PHYSICAL_ADDRESS RangeLength;
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PEI_DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE Type;
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} PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE;
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//
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// Function prototypes.
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//
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EFI_STATUS
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InstallEfiMemory (
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IN EFI_PEI_SERVICES **PeiServices,
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IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,
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IN EFI_BOOT_MODE BootMode,
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IN UINT32 TotalMemorySize
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);
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EFI_STATUS
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InstallS3Memory (
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IN EFI_PEI_SERVICES **PeiServices,
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IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,
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IN UINT32 TotalMemorySize
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);
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EFI_STATUS
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MemoryInit (
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IN EFI_PEI_SERVICES **PeiServices
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);
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EFI_STATUS
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LoadConfig (
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IN EFI_PEI_SERVICES **PeiServices,
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IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,
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IN OUT MRCParams_t *MrcData
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);
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EFI_STATUS
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SaveConfig (
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IN MRCParams_t *MrcData
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);
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VOID
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RetriveRequiredMemorySize (
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IN EFI_PEI_SERVICES **PeiServices,
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OUT UINTN *Size
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);
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EFI_STATUS
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GetMemoryMap (
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IN EFI_PEI_SERVICES **PeiServices,
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IN UINT32 TotalMemorySize,
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IN OUT PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE *MemoryMap,
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IN OUT UINT8 *NumRanges
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);
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EFI_STATUS
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ChooseRanges (
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IN OUT PEI_MEMORY_RANGE_OPTION_ROM *OptionRomMask,
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IN OUT PEI_MEMORY_RANGE_SMRAM *SmramMask,
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IN OUT PEI_MEMORY_RANGE_PCI_MEMORY *PciMemoryMask
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);
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EFI_STATUS
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GetPlatformMemorySize (
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IN EFI_PEI_SERVICES **PeiServices,
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IN EFI_BOOT_MODE BootMode,
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IN OUT UINT64 *MemorySize
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);
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EFI_STATUS
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BaseMemoryTest (
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IN EFI_PEI_SERVICES **PeiServices,
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IN EFI_PHYSICAL_ADDRESS BeginAddress,
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IN UINT64 MemoryLength,
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IN PEI_MEMORY_TEST_OP Operation,
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OUT EFI_PHYSICAL_ADDRESS *ErrorAddress
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);
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EFI_STATUS
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SetPlatformImrPolicy (
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IN EFI_PHYSICAL_ADDRESS PeiMemoryBaseAddress,
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IN UINT64 PeiMemoryLength,
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IN UINTN RequiredMemSize
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);
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VOID
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EFIAPI
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InfoPostInstallMemory (
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OUT UINT32 *RmuBaseAddressPtr OPTIONAL,
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OUT EFI_SMRAM_DESCRIPTOR **SmramDescriptorPtr OPTIONAL,
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OUT UINTN *NumSmramRegionsPtr OPTIONAL
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);
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#endif
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