mirror of https://github.com/acidanthera/audk.git
126 lines
3.4 KiB
C
126 lines
3.4 KiB
C
/** @file
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System On Chip Unit (SOCUnit) routines.
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Copyright (c) 2013-2015 Intel Corporation.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "CommonHeader.h"
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/** Early initialisation of the SOC Unit
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@retval EFI_SUCCESS Operation success.
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**/
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EFI_STATUS
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EFIAPI
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SocUnitEarlyInitialisation (
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VOID
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)
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{
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UINT32 NewValue;
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//
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// Set the mixer load resistance
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//
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NewValue = QNCPortIORead (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0);
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NewValue &= OCFGPIMIXLOAD_1_0_MASK;
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QNCPortIOWrite (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0, NewValue);
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NewValue = QNCPortIORead (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1);
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NewValue &= OCFGPIMIXLOAD_1_0_MASK;
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QNCPortIOWrite (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1, NewValue);
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return EFI_SUCCESS;
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}
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/** Tasks to release PCI controller from reset pre wait for PLL Lock.
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@retval EFI_SUCCESS Operation success.
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**/
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EFI_STATUS
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EFIAPI
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SocUnitReleasePcieControllerPreWaitPllLock (
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IN CONST EFI_PLATFORM_TYPE PlatformType
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)
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{
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UINT32 NewValue;
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//
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// Assert PERST# and validate time assertion time.
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//
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PlatformPERSTAssert (PlatformType);
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ASSERT (PCIEXP_PERST_MIN_ASSERT_US <= (PCIEXP_DELAY_US_POST_CMNRESET_RESET + PCIEXP_DELAY_US_WAIT_PLL_LOCK + PCIEXP_DELAY_US_POST_SBI_RESET));
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//
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// PHY Common lane reset.
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//
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NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);
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NewValue |= SOCCLKEN_CONFIG_PHY_I_CMNRESET_L;
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QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);
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//
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// Wait post common lane reset.
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//
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MicroSecondDelay (PCIEXP_DELAY_US_POST_CMNRESET_RESET);
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//
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// PHY Sideband interface reset.
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// Controller main reset
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//
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NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);
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NewValue |= (SOCCLKEN_CONFIG_SBI_RST_100_CORE_B | SOCCLKEN_CONFIG_PHY_I_SIDE_RST_L);
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QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);
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return EFI_SUCCESS;
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}
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/** Tasks to release PCI controller from reset after PLL has locked
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@retval EFI_SUCCESS Operation success.
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**/
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EFI_STATUS
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EFIAPI
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SocUnitReleasePcieControllerPostPllLock (
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IN CONST EFI_PLATFORM_TYPE PlatformType
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)
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{
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UINT32 NewValue;
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//
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// Controller sideband interface reset.
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//
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NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);
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NewValue |= SOCCLKEN_CONFIG_SBI_BB_RST_B;
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QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);
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//
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// Wait post sideband interface reset.
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//
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MicroSecondDelay (PCIEXP_DELAY_US_POST_SBI_RESET);
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//
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// Deassert PERST#.
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//
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PlatformPERSTDeAssert (PlatformType);
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//
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// Wait post de assert PERST#.
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//
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MicroSecondDelay (PCIEXP_DELAY_US_POST_PERST_DEASSERT);
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//
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// Controller primary interface reset.
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//
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NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);
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NewValue |= SOCCLKEN_CONFIG_BB_RST_B;
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QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);
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return EFI_SUCCESS;
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}
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