mirror of https://github.com/acidanthera/audk.git
188 lines
6.2 KiB
C
188 lines
6.2 KiB
C
/** @file
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*
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* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#ifndef __PL011_UART_H__
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#define __PL011_UART_H__
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#include <Uefi.h>
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#include <Protocol/SerialIo.h>
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// PL011 Registers
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#define UARTDR 0x000
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#define UARTRSR 0x004
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#define UARTECR 0x004
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#define UARTFR 0x018
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#define UARTILPR 0x020
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#define UARTIBRD 0x024
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#define UARTFBRD 0x028
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#define UARTLCR_H 0x02C
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#define UARTCR 0x030
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#define UARTIFLS 0x034
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#define UARTIMSC 0x038
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#define UARTRIS 0x03C
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#define UARTMIS 0x040
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#define UARTICR 0x044
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#define UARTDMACR 0x048
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// Data status bits
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#define UART_DATA_ERROR_MASK 0x0F00
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// Status reg bits
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#define UART_STATUS_ERROR_MASK 0x0F
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// Flag reg bits
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#define PL011_UARTFR_RI (1 << 8) // Ring indicator
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#define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty
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#define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full
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#define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full
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#define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty
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#define PL011_UARTFR_BUSY (1 << 3) // UART busy
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#define PL011_UARTFR_DCD (1 << 2) // Data carrier detect
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#define PL011_UARTFR_DSR (1 << 1) // Data set ready
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#define PL011_UARTFR_CTS (1 << 0) // Clear to send
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// Flag reg bits - alternative names
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#define UART_TX_EMPTY_FLAG_MASK PL011_UARTFR_TXFE
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#define UART_RX_FULL_FLAG_MASK PL011_UARTFR_RXFF
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#define UART_TX_FULL_FLAG_MASK PL011_UARTFR_TXFF
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#define UART_RX_EMPTY_FLAG_MASK PL011_UARTFR_RXFE
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#define UART_BUSY_FLAG_MASK PL011_UARTFR_BUSY
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// Control reg bits
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#define PL011_UARTCR_CTSEN (1 << 15) // CTS hardware flow control enable
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#define PL011_UARTCR_RTSEN (1 << 14) // RTS hardware flow control enable
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#define PL011_UARTCR_RTS (1 << 11) // Request to send
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#define PL011_UARTCR_DTR (1 << 10) // Data transmit ready.
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#define PL011_UARTCR_RXE (1 << 9) // Receive enable
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#define PL011_UARTCR_TXE (1 << 8) // Transmit enable
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#define PL011_UARTCR_LBE (1 << 7) // Loopback enable
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#define PL011_UARTCR_UARTEN (1 << 0) // UART Enable
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// Line Control Register Bits
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#define PL011_UARTLCR_H_SPS (1 << 7) // Stick parity select
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#define PL011_UARTLCR_H_WLEN_8 (3 << 5)
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#define PL011_UARTLCR_H_WLEN_7 (2 << 5)
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#define PL011_UARTLCR_H_WLEN_6 (1 << 5)
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#define PL011_UARTLCR_H_WLEN_5 (0 << 5)
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#define PL011_UARTLCR_H_FEN (1 << 4) // FIFOs Enable
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#define PL011_UARTLCR_H_STP2 (1 << 3) // Two stop bits select
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#define PL011_UARTLCR_H_EPS (1 << 2) // Even parity select
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#define PL011_UARTLCR_H_PEN (1 << 1) // Parity Enable
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#define PL011_UARTLCR_H_BRK (1 << 0) // Send break
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/*
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Programmed hardware of Serial port.
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@return Always return EFI_UNSUPPORTED.
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**/
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RETURN_STATUS
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EFIAPI
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PL011UartInitializePort (
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IN OUT UINTN UartBase,
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IN OUT UINT64 *BaudRate,
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IN OUT UINT32 *ReceiveFifoDepth,
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IN OUT EFI_PARITY_TYPE *Parity,
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IN OUT UINT8 *DataBits,
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IN OUT EFI_STOP_BITS_TYPE *StopBits
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);
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/**
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Set the serial device control bits.
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@param UartBase The base address of the PL011 UART.
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@param Control Control bits which are to be set on the serial device.
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@retval EFI_SUCCESS The new control bits were set on the serial device.
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@retval EFI_UNSUPPORTED The serial device does not support this operation.
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@retval EFI_DEVICE_ERROR The serial device is not functioning correctly.
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**/
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RETURN_STATUS
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EFIAPI
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PL011UartSetControl (
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IN UINTN UartBase,
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IN UINT32 Control
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);
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/**
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Get the serial device control bits.
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@param UartBase The base address of the PL011 UART.
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@param Control Control signals read from the serial device.
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@retval EFI_SUCCESS The control bits were read from the serial device.
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@retval EFI_DEVICE_ERROR The serial device is not functioning correctly.
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**/
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RETURN_STATUS
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EFIAPI
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PL011UartGetControl (
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IN UINTN UartBase,
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OUT UINT32 *Control
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);
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/**
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Write data to serial device.
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@param Buffer Point of data buffer which need to be written.
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@param NumberOfBytes Number of output bytes which are cached in Buffer.
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@retval 0 Write data failed.
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@retval !0 Actual number of bytes written to serial device.
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**/
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UINTN
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EFIAPI
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PL011UartWrite (
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IN UINTN UartBase,
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IN UINT8 *Buffer,
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IN UINTN NumberOfBytes
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);
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/**
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Read data from serial device and save the data in buffer.
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@param Buffer Point of data buffer which need to be written.
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@param NumberOfBytes Number of output bytes which are cached in Buffer.
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@retval 0 Read data failed.
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@retval !0 Actual number of bytes read from serial device.
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**/
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UINTN
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EFIAPI
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PL011UartRead (
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IN UINTN UartBase,
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OUT UINT8 *Buffer,
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IN UINTN NumberOfBytes
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);
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/**
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Check to see if any data is available to be read from the debug device.
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@retval EFI_SUCCESS At least one byte of data is available to be read
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@retval EFI_NOT_READY No data is available to be read
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@retval EFI_DEVICE_ERROR The serial device is not functioning properly
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**/
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BOOLEAN
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EFIAPI
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PL011UartPoll (
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IN UINTN UartBase
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);
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#endif
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