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4059386c70
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
181 lines
4.0 KiB
NASM
181 lines
4.0 KiB
NASM
//------------------------------------------------------------------------------
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//
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// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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// Copyright (c) 2018, Pete Batard. All rights reserved.<BR>
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//
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// SPDX-License-Identifier: BSD-2-Clause-Patent
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//
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//------------------------------------------------------------------------------
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EXPORT __aeabi_uidiv
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EXPORT __aeabi_uidivmod
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EXPORT __aeabi_idiv
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EXPORT __aeabi_idivmod
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EXPORT __rt_udiv
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EXPORT __rt_sdiv
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AREA Math, CODE, READONLY
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;
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;UINT32
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;EFIAPI
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;__aeabi_uidivmod (
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; IN UINT32 Dividend
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; IN UINT32 Divisor
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; );
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;
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__aeabi_uidiv
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__aeabi_uidivmod
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RSBS r12, r1, r0, LSR #4
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MOV r2, #0
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BCC __arm_div4
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RSBS r12, r1, r0, LSR #8
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BCC __arm_div8
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MOV r3, #0
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B __arm_div_large
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;
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;UINT64
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;EFIAPI
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;__rt_udiv (
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; IN UINT32 Divisor,
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; IN UINT32 Dividend
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; );
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;
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__rt_udiv
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; Swap R0 and R1
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MOV r12, r0
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MOV r0, r1
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MOV r1, r12
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B __aeabi_uidivmod
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;
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;UINT64
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;EFIAPI
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;__rt_sdiv (
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; IN INT32 Divisor,
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; IN INT32 Dividend
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; );
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;
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__rt_sdiv
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; Swap R0 and R1
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MOV r12, r0
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MOV r0, r1
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MOV r1, r12
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B __aeabi_idivmod
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;
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;INT32
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;EFIAPI
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;__aeabi_idivmod (
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; IN INT32 Dividend
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; IN INT32 Divisor
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; );
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;
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__aeabi_idiv
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__aeabi_idivmod
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ORRS r12, r0, r1
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BMI __arm_div_negative
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RSBS r12, r1, r0, LSR #1
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MOV r2, #0
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BCC __arm_div1
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RSBS r12, r1, r0, LSR #4
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BCC __arm_div4
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RSBS r12, r1, r0, LSR #8
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BCC __arm_div8
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MOV r3, #0
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B __arm_div_large
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__arm_div8
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RSBS r12, r1, r0, LSR #7
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SUBCS r0, r0, r1, LSL #7
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ADC r2, r2, r2
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RSBS r12, r1, r0,LSR #6
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SUBCS r0, r0, r1, LSL #6
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ADC r2, r2, r2
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RSBS r12, r1, r0, LSR #5
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SUBCS r0, r0, r1, LSL #5
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ADC r2, r2, r2
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RSBS r12, r1, r0, LSR #4
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SUBCS r0, r0, r1, LSL #4
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ADC r2, r2, r2
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__arm_div4
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RSBS r12, r1, r0, LSR #3
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SUBCS r0, r0, r1, LSL #3
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ADC r2, r2, r2
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RSBS r12, r1, r0, LSR #2
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SUBCS r0, r0, r1, LSL #2
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ADCS r2, r2, r2
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RSBS r12, r1, r0, LSR #1
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SUBCS r0, r0, r1, LSL #1
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ADC r2, r2, r2
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__arm_div1
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SUBS r1, r0, r1
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MOVCC r1, r0
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ADC r0, r2, r2
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BX r14
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__arm_div_negative
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ANDS r2, r1, #0x80000000
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RSBMI r1, r1, #0
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EORS r3, r2, r0, ASR #32
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RSBCS r0, r0, #0
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RSBS r12, r1, r0, LSR #4
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BCC label1
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RSBS r12, r1, r0, LSR #8
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BCC label2
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__arm_div_large
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LSL r1, r1, #6
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RSBS r12, r1, r0, LSR #8
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ORR r2, r2, #0xfc000000
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BCC label2
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LSL r1, r1, #6
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RSBS r12, r1, r0, LSR #8
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ORR r2, r2, #0x3f00000
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BCC label2
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LSL r1, r1, #6
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RSBS r12, r1, r0, LSR #8
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ORR r2, r2, #0xfc000
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ORRCS r2, r2, #0x3f00
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LSLCS r1, r1, #6
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RSBS r12, r1, #0
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BCS __aeabi_idiv0
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label3
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LSRCS r1, r1, #6
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label2
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RSBS r12, r1, r0, LSR #7
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SUBCS r0, r0, r1, LSL #7
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ADC r2, r2, r2
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RSBS r12, r1, r0, LSR #6
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SUBCS r0, r0, r1, LSL #6
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ADC r2, r2, r2
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RSBS r12, r1, r0, LSR #5
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SUBCS r0, r0, r1, LSL #5
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ADC r2, r2, r2
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RSBS r12, r1, r0, LSR #4
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SUBCS r0, r0, r1, LSL #4
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ADC r2, r2, r2
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label1
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RSBS r12, r1, r0, LSR #3
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SUBCS r0, r0, r1, LSL #3
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ADC r2, r2, r2
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RSBS r12, r1, r0, LSR #2
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SUBCS r0, r0, r1, LSL #2
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ADCS r2, r2, r2
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BCS label3
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RSBS r12, r1, r0, LSR #1
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SUBCS r0, r0, r1, LSL #1
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ADC r2, r2, r2
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SUBS r1, r0, r1
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MOVCC r1, r0
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ADC r0, r2, r2
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ASRS r3, r3, #31
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RSBMI r0, r0, #0
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RSBCS r1, r1, #0
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BX r14
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; What to do about division by zero? For now, just return.
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__aeabi_idiv0
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BX r14
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END
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