mirror of https://github.com/acidanthera/audk.git
142 lines
4.2 KiB
ArmAsm
142 lines
4.2 KiB
ArmAsm
#------------------------------------------------------------------------------
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#
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# Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php.
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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# Module Name:
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#
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# SmmInit.S
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#
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# Abstract:
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#
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# Functions for relocating SMBASE's for all processors
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#
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#------------------------------------------------------------------------------
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ASM_GLOBAL ASM_PFX(gSmmCr0)
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ASM_GLOBAL ASM_PFX(gSmmCr3)
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ASM_GLOBAL ASM_PFX(gSmmCr4)
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ASM_GLOBAL ASM_PFX(gSmmJmpAddr)
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ASM_GLOBAL ASM_PFX(gcSmmInitTemplate)
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ASM_GLOBAL ASM_PFX(gcSmmInitSize)
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ASM_GLOBAL ASM_PFX(mRebasedFlagAddr32)
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ASM_GLOBAL ASM_PFX(SmmRelocationSemaphoreComplete)
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ASM_GLOBAL ASM_PFX(SmmRelocationSemaphoreComplete32)
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ASM_GLOBAL ASM_PFX(mSmmRelocationOriginalAddressPtr32)
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ASM_GLOBAL ASM_PFX(gSmmInitStack)
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ASM_GLOBAL ASM_PFX(gcSmiInitGdtr)
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.text
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ASM_PFX(gcSmiInitGdtr):
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.word 0
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.quad 0
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SmmStartup:
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.byte 0x66,0xb8 # mov eax, imm32
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ASM_PFX(gSmmCr3): .space 4
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movq %rax, %cr3
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.byte 0x66,0x2e
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lgdt (ASM_PFX(gcSmiInitGdtr) - SmmStartup)(%ebp)
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.byte 0x66,0xb8 # mov eax, imm32
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ASM_PFX(gSmmCr4): .space 4
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orb $2, %ah # enable XMM registers access
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movq %rax, %cr4
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.byte 0x66
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movl $0xc0000080,%ecx # IA32_EFER MSR
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rdmsr
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orb $1,%ah # set LME bit
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wrmsr
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.byte 0x66,0xb8 # mov eax, imm32
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ASM_PFX(gSmmCr0): .space 4
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movq %rax, %cr0
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.byte 0x66,0xea # far jmp to long mode
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ASM_PFX(gSmmJmpAddr): .quad LongMode
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LongMode: # long-mode starts here
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.byte 0x48,0xbc # mov rsp, imm64
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ASM_PFX(gSmmInitStack): .space 8
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andw $0xfff0, %sp # make sure RSP is 16-byte aligned
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#
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# Accoring to X64 calling convention, XMM0~5 are volatile, we need to save
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# them before calling C-function.
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#
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subq $0x60, %rsp
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movdqa %xmm0, 0x0(%rsp)
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movdqa %xmm1, 0x10(%rsp)
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movdqa %xmm2, 0x20(%rsp)
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movdqa %xmm3, 0x30(%rsp)
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movdqa %xmm4, 0x40(%rsp)
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movdqa %xmm5, 0x50(%rsp)
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addq $-0x20, %rsp
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call ASM_PFX(SmmInitHandler)
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addq $0x20, %rsp
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#
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# Restore XMM0~5 after calling C-function.
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#
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movdqa 0x0(%rsp), %xmm0
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movdqa 0x10(%rsp), %xmm1
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movdqa 0x20(%rsp), %xmm2
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movdqa 0x30(%rsp), %xmm3
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movdqa 0x40(%rsp), %xmm4
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movdqa 0x50(%rsp), %xmm5
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rsm
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ASM_PFX(gcSmmInitTemplate):
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_SmmInitTemplate:
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.byte 0x66,0x2e,0x8b,0x2e # mov ebp, cs:[@F]
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.word L1 - _SmmInitTemplate + 0x8000
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.byte 0x66, 0x81, 0xed, 0, 0, 3, 0 # sub ebp, 0x30000
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jmp *%bp # jmp ebp actually
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L1:
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.quad SmmStartup
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ASM_PFX(gcSmmInitSize): .word . - ASM_PFX(gcSmmInitTemplate)
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ASM_PFX(SmmRelocationSemaphoreComplete):
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# Create a simple stack frame to store RAX and the original RSM location
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pushq %rax # Used to store return address
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pushq %rax
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# Load the original RSM location onto stack
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movabsq $ASM_PFX(mSmmRelocationOriginalAddress), %rax
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movq (%rax), %rax
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movq %rax, 0x08(%rsp)
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# Update rebase flag
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movabsq $ASM_PFX(mRebasedFlag), %rax
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movq (%rax), %rax
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movb $1, (%rax)
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#restore RAX and return to original RSM location
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popq %rax
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retq
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#
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# Semaphore code running in 32-bit mode
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#
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ASM_PFX(SmmRelocationSemaphoreComplete32):
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#
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# movb $1, ()
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#
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.byte 0xc6, 0x05
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ASM_PFX(mRebasedFlagAddr32):
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.long 0
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.byte 1
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#
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# jmpd ()
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#
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.byte 0xff, 0x25
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ASM_PFX(mSmmRelocationOriginalAddressPtr32):
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.long 0
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