mirror of https://github.com/acidanthera/audk.git
143 lines
4.5 KiB
C
143 lines
4.5 KiB
C
/** @file
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ArmGicArchLib library class implementation for DT based virt platforms
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Copyright (c) 2015 - 2016, Linaro Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Base.h>
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#include <Uefi.h>
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#include <Library/ArmGicLib.h>
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#include <Library/ArmGicArchLib.h>
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#include <Library/BaseLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Protocol/FdtClient.h>
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STATIC ARM_GIC_ARCH_REVISION mGicArchRevision;
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RETURN_STATUS
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EFIAPI
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ArmVirtGicArchLibConstructor (
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VOID
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)
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{
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UINT32 IccSre;
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FDT_CLIENT_PROTOCOL *FdtClient;
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CONST UINT64 *Reg;
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UINT32 RegElemSize, RegSize;
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UINTN GicRevision;
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EFI_STATUS Status;
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UINT64 DistBase, CpuBase, RedistBase;
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Status = gBS->LocateProtocol (&gFdtClientProtocolGuid, NULL,
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(VOID **)&FdtClient);
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ASSERT_EFI_ERROR (Status);
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GicRevision = 2;
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Status = FdtClient->FindCompatibleNodeReg (FdtClient, "arm,cortex-a15-gic",
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(CONST VOID **)&Reg, &RegElemSize, &RegSize);
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if (Status == EFI_NOT_FOUND) {
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GicRevision = 3;
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Status = FdtClient->FindCompatibleNodeReg (FdtClient, "arm,gic-v3",
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(CONST VOID **)&Reg, &RegElemSize, &RegSize);
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}
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if (EFI_ERROR (Status)) {
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return Status;
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}
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switch (GicRevision) {
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case 3:
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//
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// The GIC v3 DT binding describes a series of at least 3 physical (base
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// addresses, size) pairs: the distributor interface (GICD), at least one
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// redistributor region (GICR) containing dedicated redistributor
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// interfaces for all individual CPUs, and the CPU interface (GICC).
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// Under virtualization, we assume that the first redistributor region
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// listed covers the boot CPU. Also, our GICv3 driver only supports the
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// system register CPU interface, so we can safely ignore the MMIO version
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// which is listed after the sequence of redistributor interfaces.
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// This means we are only interested in the first two memory regions
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// supplied, and ignore everything else.
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//
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ASSERT (RegSize >= 32);
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// RegProp[0..1] == { GICD base, GICD size }
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DistBase = SwapBytes64 (Reg[0]);
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ASSERT (DistBase < MAX_UINT32);
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// RegProp[2..3] == { GICR base, GICR size }
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RedistBase = SwapBytes64 (Reg[2]);
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ASSERT (RedistBase < MAX_UINT32);
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PcdSet64 (PcdGicDistributorBase, DistBase);
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PcdSet64 (PcdGicRedistributorsBase, RedistBase);
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DEBUG ((EFI_D_INFO, "Found GIC v3 (re)distributor @ 0x%Lx (0x%Lx)\n",
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DistBase, RedistBase));
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//
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// The default implementation of ArmGicArchLib is responsible for enabling
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// the system register interface on the GICv3 if one is found. So let's do
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// the same here.
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//
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IccSre = ArmGicV3GetControlSystemRegisterEnable ();
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if (!(IccSre & ICC_SRE_EL2_SRE)) {
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ArmGicV3SetControlSystemRegisterEnable (IccSre | ICC_SRE_EL2_SRE);
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IccSre = ArmGicV3GetControlSystemRegisterEnable ();
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}
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//
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// Unlike the default implementation, there is no fall through to GICv2
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// mode if this GICv3 cannot be driven in native mode due to the fact
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// that the System Register interface is unavailable.
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//
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ASSERT (IccSre & ICC_SRE_EL2_SRE);
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mGicArchRevision = ARM_GIC_ARCH_REVISION_3;
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break;
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case 2:
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ASSERT (RegSize == 32);
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DistBase = SwapBytes64 (Reg[0]);
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CpuBase = SwapBytes64 (Reg[2]);
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ASSERT (DistBase < MAX_UINT32);
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ASSERT (CpuBase < MAX_UINT32);
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PcdSet64 (PcdGicDistributorBase, DistBase);
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PcdSet64 (PcdGicInterruptInterfaceBase, CpuBase);
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DEBUG ((EFI_D_INFO, "Found GIC @ 0x%Lx/0x%Lx\n", DistBase, CpuBase));
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mGicArchRevision = ARM_GIC_ARCH_REVISION_2;
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break;
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default:
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DEBUG ((EFI_D_ERROR, "%a: No GIC revision specified!\n", __FUNCTION__));
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return RETURN_NOT_FOUND;
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}
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return RETURN_SUCCESS;
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}
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ARM_GIC_ARCH_REVISION
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EFIAPI
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ArmGicGetSupportedArchRevision (
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VOID
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)
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{
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return mGicArchRevision;
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}
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