mirror of https://github.com/acidanthera/audk.git
105 lines
2.9 KiB
NASM
105 lines
2.9 KiB
NASM
//
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// Copyright (c) 2011, ARM Limited. All rights reserved.
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//
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#include <AutoGen.h>
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#include <AsmMacroIoLib.h>
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#include <Base.h>
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#include <Library/PcdLib.h>
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#include <Library/ArmPlatformLib.h>
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INCLUDE AsmMacroIoLib.inc
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IMPORT CEntryPoint
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IMPORT ArmPlatformIsMemoryInitialized
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IMPORT ArmPlatformInitializeBootMemory
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IMPORT ArmDisableInterrupts
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IMPORT ArmDisableCachesAndMmu
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IMPORT ArmWriteVBar
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IMPORT ArmReadMpidr
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IMPORT SecVectorTable
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EXPORT _ModuleEntryPoint
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#if (FixedPcdGet32(PcdMPCoreSupport))
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IMPORT ArmIsScuEnable
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#endif
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PRESERVE8
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AREA SecEntryPoint, CODE, READONLY
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StartupAddr DCD CEntryPoint
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_ModuleEntryPoint
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//Set VBAR to the start of the exception vectors in Secure Mode
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ldr r0, =SecVectorTable
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blx ArmWriteVBar
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// First ensure all interrupts are disabled
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blx ArmDisableInterrupts
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// Ensure that the MMU and caches are off
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blx ArmDisableCachesAndMmu
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_IdentifyCpu
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// Identify CPU ID
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bl ArmReadMpidr
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and r5, r0, #0xf
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//get ID of this CPU in Multicore system
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cmp r5, #0
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// Only the primary core initialize the memory (SMC)
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beq _InitMem
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#if (FixedPcdGet32(PcdMPCoreSupport))
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// ... The secondary cores wait for SCU to be enabled
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_WaitForEnabledScu
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bl ArmIsScuEnable
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tst r1, #1
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beq _WaitForEnabledScu
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b _SetupStack
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#endif
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_InitMem
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bl ArmPlatformIsMemoryInitialized
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bne _SetupStack
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// Initialize Init Memory
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bl ArmPlatformInitializeBootMemory
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// Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
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mov r5, #0
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_SetupStack
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// Setup Stack for the 4 CPU cores
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//Read Stack Base address from PCD
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LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
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// Read Stack size from PCD
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LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecStackSize), r2)
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// Calcuate Stack Pointer reg value using Stack size and CPU ID.
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mov r3,r5 // r3 = core_id
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mul r3,r3,r2 // r3 = core_id * stack_size = offset from the stack base
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add r3,r3,r1 // r3 = stack_base + offset
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mov sp, r3
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// Move sec startup address into a data register
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// ensure we're jumping to FV version of the code (not boot remapped alias)
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ldr r3, StartupAddr
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// Jump to SEC C code
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// r0 = core_id
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mov r0, r5
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blx r3
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END
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