mirror of https://github.com/acidanthera/audk.git
167 lines
3.7 KiB
C
167 lines
3.7 KiB
C
/** @file
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SMM profile internal header file.
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Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2020, AMD Incorporated. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _SMM_PROFILE_INTERNAL_H_
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#define _SMM_PROFILE_INTERNAL_H_
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#include <Protocol/SmmReadyToLock.h>
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#include <Library/UefiRuntimeServicesTableLib.h>
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#include <Library/DxeServicesTableLib.h>
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#include <Library/CpuLib.h>
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#include <IndustryStandard/Acpi.h>
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#include "SmmProfileArch.h"
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//
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// Configure the SMM_PROFILE DTS region size
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//
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#define SMM_PROFILE_DTS_SIZE (4 * 1024 * 1024) // 4M
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#define MAX_PF_PAGE_COUNT 0x2
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#define PEBS_RECORD_NUMBER 0x2
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#define MAX_PF_ENTRY_COUNT 10
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//
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// This MACRO just enable unit test for the profile
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// Please disable it.
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//
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#define IA32_PF_EC_ID (1u << 4)
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#define SMM_PROFILE_NAME L"SmmProfileData"
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//
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// CPU generic definition
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//
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#define CPUID1_EDX_XD_SUPPORT 0x100000
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#define MSR_EFER 0xc0000080
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#define MSR_EFER_XD 0x800
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#define CPUID1_EDX_BTS_AVAILABLE 0x200000
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#define DR6_SINGLE_STEP 0x4000
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#define RFLAG_TF 0x100
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#define MSR_DEBUG_CTL 0x1D9
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#define MSR_DEBUG_CTL_LBR 0x1
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#define MSR_DEBUG_CTL_TR 0x40
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#define MSR_DEBUG_CTL_BTS 0x80
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#define MSR_DEBUG_CTL_BTINT 0x100
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#define MSR_DS_AREA 0x600
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#define HEAP_GUARD_NONSTOP_MODE \
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((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT6|BIT3|BIT2)) > BIT6)
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#define NULL_DETECTION_NONSTOP_MODE \
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((PcdGet8 (PcdNullPointerDetectionPropertyMask) & (BIT6|BIT1)) > BIT6)
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typedef struct {
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EFI_PHYSICAL_ADDRESS Base;
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EFI_PHYSICAL_ADDRESS Top;
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} MEMORY_RANGE;
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typedef struct {
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MEMORY_RANGE Range;
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BOOLEAN Present;
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BOOLEAN Nx;
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} MEMORY_PROTECTION_RANGE;
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typedef struct {
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UINT64 HeaderSize;
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UINT64 MaxDataEntries;
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UINT64 MaxDataSize;
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UINT64 CurDataEntries;
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UINT64 CurDataSize;
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UINT64 TsegStart;
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UINT64 TsegSize;
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UINT64 NumSmis;
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UINT64 NumCpus;
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} SMM_PROFILE_HEADER;
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typedef struct {
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UINT64 SmiNum;
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UINT64 CpuNum;
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UINT64 ApicId;
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UINT64 ErrorCode;
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UINT64 Instruction;
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UINT64 Address;
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UINT64 SmiCmd;
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} SMM_PROFILE_ENTRY;
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extern SMM_S3_RESUME_STATE *mSmmS3ResumeState;
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extern UINTN gSmiExceptionHandlers[];
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extern BOOLEAN mXdSupported;
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X86_ASSEMBLY_PATCH_LABEL gPatchXdSupported;
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X86_ASSEMBLY_PATCH_LABEL gPatchMsrIa32MiscEnableSupported;
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extern UINTN *mPFEntryCount;
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extern UINT64 (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT];
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extern UINT64 *(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUNT];
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//
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// Internal functions
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//
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/**
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Update IDT table to replace page fault handler and INT 1 handler.
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**/
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VOID
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InitIdtr (
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VOID
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);
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/**
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Check if the memory address will be mapped by 4KB-page.
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@param Address The address of Memory.
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**/
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BOOLEAN
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IsAddressSplit (
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IN EFI_PHYSICAL_ADDRESS Address
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);
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/**
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Check if the memory address will be mapped by 4KB-page.
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@param Address The address of Memory.
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@param Nx The flag indicates if the memory is execute-disable.
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**/
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BOOLEAN
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IsAddressValid (
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IN EFI_PHYSICAL_ADDRESS Address,
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IN BOOLEAN *Nx
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);
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/**
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Page Fault handler for SMM use.
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**/
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VOID
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SmiDefaultPFHandler (
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VOID
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);
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/**
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Clear TF in FLAGS.
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@param SystemContext A pointer to the processor context when
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the interrupt occurred on the processor.
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**/
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VOID
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ClearTrapFlag (
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IN OUT EFI_SYSTEM_CONTEXT SystemContext
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);
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#endif // _SMM_PROFILE_H_
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