mirror of https://github.com/acidanthera/audk.git
328 lines
8.5 KiB
C
328 lines
8.5 KiB
C
/** @file
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Common Lib function for QNC internal network access.
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Copyright (c) 2013-2015 Intel Corporation.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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//
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// The package level header files this module uses
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//
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#include <Uefi.h>
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#include <IntelQNCRegs.h>
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#include <Library/QNCAccessLib.h>
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#include <Library/DebugLib.h>
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#include <IndustryStandard/Pci22.h>
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UINT32
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EFIAPI
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QNCPortRead(
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UINT8 Port,
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UINT32 RegAddress
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)
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{
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McD0PciCfg32 (QNC_ACCESS_PORT_MEA) = (RegAddress & 0xFFFFFF00);
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McD0PciCfg32 (QNC_ACCESS_PORT_MCR) = MESSAGE_READ_DW (Port, RegAddress);
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return McD0PciCfg32 (QNC_ACCESS_PORT_MDR);
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}
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VOID
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EFIAPI
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QNCPortWrite (
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UINT8 Port,
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UINT32 RegAddress,
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UINT32 WriteValue
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)
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{
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McD0PciCfg32 (QNC_ACCESS_PORT_MDR) = WriteValue;
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McD0PciCfg32 (QNC_ACCESS_PORT_MEA) = (RegAddress & 0xFFFFFF00);
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McD0PciCfg32 (QNC_ACCESS_PORT_MCR) = MESSAGE_WRITE_DW (Port, RegAddress);
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}
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UINT32
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EFIAPI
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QNCAltPortRead (
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UINT8 Port,
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UINT32 RegAddress
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)
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{
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McD0PciCfg32 (QNC_ACCESS_PORT_MEA) = (RegAddress & 0xFFFFFF00);
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McD0PciCfg32 (QNC_ACCESS_PORT_MCR) = ALT_MESSAGE_READ_DW (Port, RegAddress);
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return McD0PciCfg32 (QNC_ACCESS_PORT_MDR);
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}
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VOID
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EFIAPI
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QNCAltPortWrite (
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UINT8 Port,
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UINT32 RegAddress,
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UINT32 WriteValue
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)
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{
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McD0PciCfg32 (QNC_ACCESS_PORT_MDR) = WriteValue;
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McD0PciCfg32 (QNC_ACCESS_PORT_MEA) = (RegAddress & 0xFFFFFF00);
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McD0PciCfg32 (QNC_ACCESS_PORT_MCR) = ALT_MESSAGE_WRITE_DW (Port, RegAddress);
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}
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UINT32
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EFIAPI
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QNCPortIORead(
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UINT8 Port,
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UINT32 RegAddress
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)
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{
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McD0PciCfg32 (QNC_ACCESS_PORT_MEA) = (RegAddress & 0xFFFFFF00);
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McD0PciCfg32 (QNC_ACCESS_PORT_MCR) = MESSAGE_IO_READ_DW (Port, RegAddress);
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return McD0PciCfg32 (QNC_ACCESS_PORT_MDR);
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}
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VOID
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EFIAPI
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QNCPortIOWrite (
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UINT8 Port,
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UINT32 RegAddress,
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UINT32 WriteValue
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)
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{
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McD0PciCfg32 (QNC_ACCESS_PORT_MDR) = WriteValue;
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McD0PciCfg32 (QNC_ACCESS_PORT_MEA) = (RegAddress & 0xFFFFFF00);
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McD0PciCfg32 (QNC_ACCESS_PORT_MCR) = MESSAGE_IO_WRITE_DW (Port, RegAddress);
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}
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RETURN_STATUS
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EFIAPI
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QNCMmIoWrite (
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UINT32 MmIoAddress,
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QNC_MEM_IO_WIDTH Width,
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UINT32 DataNumber,
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VOID *pData
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)
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/*++
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Routine Description:
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This is for the special consideration for QNC MMIO write, as required by FWG, a reading must be performed after MMIO writing
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to ensure the expected write is processed and data is flushed into chipset
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Arguments:
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Row -- row number to be cleared ( start from 1 )
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Returns:
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EFI_SUCCESS
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--*/
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{
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RETURN_STATUS Status;
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UINTN Index;
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Status = RETURN_SUCCESS;
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for (Index =0; Index < DataNumber; Index++) {
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switch (Width) {
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case QNCMmioWidthUint8:
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QNCMmio8 (MmIoAddress, 0) = ((UINT8 *)pData)[Index];
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if (QNCMmio8 (MmIoAddress, 0) != ((UINT8*)pData)[Index]) {
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Status = RETURN_DEVICE_ERROR;
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break;
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}
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break;
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case QNCMmioWidthUint16:
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QNCMmio16 (MmIoAddress, 0) = ((UINT16 *)pData)[Index];
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if (QNCMmio16 (MmIoAddress, 0) != ((UINT16 *)pData)[Index]) {
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Status = RETURN_DEVICE_ERROR;
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break;
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}
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break;
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case QNCMmioWidthUint32:
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QNCMmio32 (MmIoAddress, 0) = ((UINT32 *)pData)[Index];
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if (QNCMmio32 (MmIoAddress, 0) != ((UINT32 *)pData)[Index]) {
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Status = RETURN_DEVICE_ERROR;
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break;
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}
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break;
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case QNCMmioWidthUint64:
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QNCMmio64 (MmIoAddress, 0) = ((UINT64 *)pData)[Index];
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if (QNCMmio64 (MmIoAddress, 0) != ((UINT64 *)pData)[Index]) {
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Status = RETURN_DEVICE_ERROR;
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break;
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}
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break;
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default:
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break;
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}
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}
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return Status;
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}
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UINT32
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EFIAPI
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QncHsmmcRead (
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VOID
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)
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{
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return QNCPortRead (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HSMMC);
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}
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VOID
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EFIAPI
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QncHsmmcWrite (
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UINT32 WriteValue
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)
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{
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UINT16 DeviceId;
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UINT32 Data32;
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//
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// Check what Soc we are running on (read Host bridge DeviceId)
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//
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DeviceId = QNCMmPci16(0, MC_BUS, MC_DEV, MC_FUN, PCI_DEVICE_ID_OFFSET);
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if (DeviceId == QUARK2_MC_DEVICE_ID) {
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//
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// Disable HSMMC configuration
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//
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Data32 = QncHsmmcRead ();
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Data32 &= ~SMM_CTL_EN;
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QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HSMMC, Data32);
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//
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// Validate HSMMC configuration is disabled
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//
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Data32 = QncHsmmcRead ();
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ASSERT((Data32 & SMM_CTL_EN) == 0);
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//
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// Enable HSMMC configuration
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//
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WriteValue |= SMM_CTL_EN;
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}
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//
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// Write the register value
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//
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QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HSMMC, WriteValue);
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if (DeviceId == QUARK2_MC_DEVICE_ID) {
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//
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// Validate HSMMC configuration is enabled
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//
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Data32 = QncHsmmcRead ();
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ASSERT((Data32 & SMM_CTL_EN) != 0);
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}
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}
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VOID
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EFIAPI
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QncImrWrite (
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UINT32 ImrBaseOffset,
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UINT32 ImrLow,
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UINT32 ImrHigh,
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UINT32 ImrReadMask,
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UINT32 ImrWriteMask
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)
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{
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UINT16 DeviceId;
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UINT32 Data32;
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//
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// Check what Soc we are running on (read Host bridge DeviceId)
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//
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DeviceId = QNCMmPci16(0, MC_BUS, MC_DEV, MC_FUN, PCI_DEVICE_ID_OFFSET);
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//
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// Disable IMR protection
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//
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if (DeviceId == QUARK2_MC_DEVICE_ID) {
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//
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// Disable IMR protection
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//
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Data32 = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, ImrBaseOffset+QUARK_NC_MEMORY_MANAGER_IMRXL);
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Data32 &= ~IMR_EN;
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QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, ImrBaseOffset+QUARK_NC_MEMORY_MANAGER_IMRXL, Data32);
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//
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// Validate IMR protection is disabled
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//
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Data32 = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, ImrBaseOffset+QUARK_NC_MEMORY_MANAGER_IMRXL);
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ASSERT((Data32 & IMR_EN) == 0);
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//
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// Update the IMR (IMRXL must be last as it may enable IMR violation checking)
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//
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QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, ImrBaseOffset+QUARK_NC_MEMORY_MANAGER_IMRXRM, ImrReadMask);
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QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, ImrBaseOffset+QUARK_NC_MEMORY_MANAGER_IMRXWM, ImrWriteMask);
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QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, ImrBaseOffset+QUARK_NC_MEMORY_MANAGER_IMRXH, ImrHigh);
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QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, ImrBaseOffset+QUARK_NC_MEMORY_MANAGER_IMRXL, ImrLow);
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//
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// Validate IMR protection is enabled/disabled
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//
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Data32 = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, ImrBaseOffset+QUARK_NC_MEMORY_MANAGER_IMRXL);
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ASSERT((Data32 & IMR_EN) == (ImrLow & IMR_EN));
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} else {
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//
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// Disable IMR protection (allow all access)
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//
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QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, ImrBaseOffset+QUARK_NC_MEMORY_MANAGER_IMRXRM, (UINT32)IMRX_ALL_ACCESS);
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QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, ImrBaseOffset+QUARK_NC_MEMORY_MANAGER_IMRXWM, (UINT32)IMRX_ALL_ACCESS);
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//
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// Update the IMR (IMRXRM/IMRXWM must be last as they restrict IMR access)
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//
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QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, ImrBaseOffset+QUARK_NC_MEMORY_MANAGER_IMRXL, (ImrLow & ~IMR_EN));
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QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, ImrBaseOffset+QUARK_NC_MEMORY_MANAGER_IMRXH, ImrHigh);
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QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, ImrBaseOffset+QUARK_NC_MEMORY_MANAGER_IMRXRM, ImrReadMask);
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QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, ImrBaseOffset+QUARK_NC_MEMORY_MANAGER_IMRXWM, ImrWriteMask);
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}
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}
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VOID
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EFIAPI
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QncIClkAndThenOr (
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UINT32 RegAddress,
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UINT32 AndValue,
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UINT32 OrValue
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)
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{
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UINT32 RegValue;
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//
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// Whenever an iCLK SB register (Endpoint 32h) is being programmed the access
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// should always consist of a READ from the address followed by 2 identical
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// WRITEs to that address.
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//
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RegValue = QNCAltPortRead (QUARK_ICLK_SB_PORT_ID, RegAddress);
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RegValue &= AndValue;
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RegValue |= OrValue;
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QNCAltPortWrite (QUARK_ICLK_SB_PORT_ID, RegAddress, RegValue);
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QNCAltPortWrite (QUARK_ICLK_SB_PORT_ID, RegAddress, RegValue);
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}
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VOID
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EFIAPI
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QncIClkOr (
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UINT32 RegAddress,
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UINT32 OrValue
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)
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{
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UINT32 RegValue;
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//
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// Whenever an iCLK SB register (Endpoint 32h) is being programmed the access
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// should always consist of a READ from the address followed by 2 identical
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// WRITEs to that address.
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//
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RegValue = QNCAltPortRead (QUARK_ICLK_SB_PORT_ID, RegAddress);
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RegValue |= OrValue;
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QNCAltPortWrite (QUARK_ICLK_SB_PORT_ID, RegAddress, RegValue);
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QNCAltPortWrite (QUARK_ICLK_SB_PORT_ID, RegAddress, RegValue);
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}
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