mirror of https://github.com/acidanthera/audk.git
249 lines
11 KiB
C
249 lines
11 KiB
C
/** @file
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Header file for QuarkSCSocId Ioh.
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Copyright (c) 2013-2015 Intel Corporation.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _IOH_H_
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#define _IOH_H_
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#ifndef BIT0
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#define BIT0 0x01
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#define BIT1 0x02
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#define BIT2 0x04
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#define BIT3 0x08
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#define BIT4 0x10
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#define BIT5 0x20
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#define BIT6 0x40
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#define BIT7 0x80
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#define BIT8 0x100
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#define BIT9 0x200
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#define BIT00 0x00000001
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#define BIT01 0x00000002
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#define BIT02 0x00000004
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#define BIT03 0x00000008
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#define BIT04 0x00000010
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#define BIT05 0x00000020
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#define BIT06 0x00000040
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#define BIT07 0x00000080
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#define BIT08 0x00000100
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#define BIT09 0x00000200
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#define BIT10 0x00000400
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#define BIT11 0x00000800
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#define BIT12 0x00001000
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#define BIT13 0x00002000
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#define BIT14 0x00004000
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#define BIT15 0x00008000
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#define BIT16 0x00010000
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#define BIT17 0x00020000
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#define BIT18 0x00040000
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#define BIT19 0x00080000
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#define BIT20 0x00100000
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#define BIT21 0x00200000
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#define BIT22 0x00400000
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#define BIT23 0x00800000
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#define BIT24 0x01000000
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#define BIT25 0x02000000
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#define BIT26 0x04000000
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#define BIT27 0x08000000
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#define BIT28 0x10000000
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#define BIT29 0x20000000
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#define BIT30 0x40000000
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#define BIT31 0x80000000
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#endif
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#define IOH_PCI_CFG_ADDRESS(bus,dev,func,reg) \
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((UINT32) ( (((UINTN)bus) << 24) + (((UINTN)dev) << 16) + \
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(((UINTN)func) << 8) + ((UINTN)reg) ))& 0x00000000ffffffff
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//----------------------------------------------------------------------------
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#define INTEL_VENDOR_ID 0x8086 // Intel Vendor ID
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//----------------------------------------------------------------------------
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// Pci Configuration Map Register Offsets
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//----------------------------------------------------------------------------
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#define PCI_REG_VID 0x00 // Vendor ID Register
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#define PCI_REG_DID 0x02 // Device ID Register
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#define PCI_REG_PCICMD 0x04 // PCI Command Register
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#define PCI_REG_PCISTS 0x06 // PCI Status Register
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#define PCI_REG_RID 0x08 // PCI Revision ID Register
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#define PCI_REG_PI 0x09 // Programming Interface
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#define PCI_REG_SCC 0x0a // Sub Class Code Register
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#define PCI_REG_BCC 0x0b // Base Class Code Register
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#define PCI_REG_PMLT 0x0d // Primary Master Latnecy Timer
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#define PCI_REG_HDR 0x0e // Header Type Register
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#define PCI_REG_PBUS 0x18 // Primary Bus Number Register
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#define PCI_REG_SBUS 0x19 // Secondary Bus Number Register
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#define PCI_REG_SUBUS 0x1a // Subordinate Bus Number Register
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#define PCI_REG_SMLT 0x1b // Secondary Master Latnecy Timer
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#define PCI_REG_IOBASE 0x1c // I/O base Register
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#define PCI_REG_IOLIMIT 0x1d // I/O Limit Register
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#define PCI_REG_SECSTATUS 0x1e // Secondary Status Register
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#define PCI_REG_MEMBASE 0x20 // Memory Base Register
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#define PCI_REG_MEMLIMIT 0x22 // Memory Limit Register
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#define PCI_REG_PRE_MEMBASE 0x24 // Prefretchable memory Base register
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#define PCI_REG_PRE_MEMLIMIT 0x26 // Prefretchable memory Limit register
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#define PCI_REG_SVID0 0x2c // Subsystem Vendor ID low byte
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#define PCI_REG_SVID1 0x2d // Subsystem Vendor ID high byte
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#define PCI_REG_SID0 0x2e // Subsystem ID low byte
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#define PCI_REG_SID1 0x2f // Subsystem ID high byte
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#define PCI_REG_IOBASE_U 0x30 // I/O base Upper Register
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#define PCI_REG_IOLIMIT_U 0x32 // I/O Limit Upper Register
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#define PCI_REG_INTLINE 0x3c // Interrupt Line Register
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#define PCI_REG_BRIDGE_CNTL 0x3e // Bridge Control Register
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//---------------------------------------------------------------------------
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// QuarkSCSocId Packet Hub definitions
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//---------------------------------------------------------------------------
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#define PCIE_BRIDGE_VID_DID 0x88008086
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//---------------------------------------------------------------------------
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// Quark South Cluster definitions.
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//---------------------------------------------------------------------------
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#define IOH_BUS 0
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#define IOH_PCI_IOSF2AHB_0_DEV_NUM 0x14
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#define IOH_PCI_IOSF2AHB_0_MAX_FUNCS 7
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#define IOH_PCI_IOSF2AHB_1_DEV_NUM 0x15
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#define IOH_PCI_IOSF2AHB_1_MAX_FUNCS 3
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//---------------------------------------------------------------------------
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// Quark South Cluster USB definitions.
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//---------------------------------------------------------------------------
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#define IOH_USB_BUS_NUMBER IOH_BUS
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#define IOH_USB_CONTROLLER_MMIO_RANGE 0x1000
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#define IOH_MAX_OHCI_USB_CONTROLLERS 1
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#define IOH_MAX_EHCI_USB_CONTROLLERS 1
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#define IOH_MAX_USBDEVICE_USB_CONTROLLERS 1
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#define R_IOH_USB_VENDOR_ID 0x00
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#define V_IOH_USB_VENDOR_ID INTEL_VENDOR_ID
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#define R_IOH_USB_DEVICE_ID 0x02
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#define R_IOH_USB_COMMAND 0x04
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#define B_IOH_USB_COMMAND_BME BIT2
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#define B_IOH_USB_COMMAND_MSE BIT1
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#define B_IOH_USB_COMMAND_ISE BIT0
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#define R_IOH_USB_MEMBAR 0x10
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#define B_IOH_USB_MEMBAR_ADDRESS_MASK 0xFFFFF000 // [31:12].
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#define R_IOH_USB_OHCI_HCCABAR 0x18
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//---------------------------------------------------------------------------
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// Quark South Cluster OHCI definitions
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//---------------------------------------------------------------------------
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#define IOH_USB_OHCI_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM
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#define IOH_OHCI_FUNCTION_NUMBER 0x04
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//---------------------------------------------------------------------------
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// Quark South Cluster EHCI definitions
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//---------------------------------------------------------------------------
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#define IOH_USB_EHCI_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM
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#define IOH_EHCI_FUNCTION_NUMBER 0x03
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//
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// EHCI memory mapped registers offset from memory BAR0.
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//
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#define R_IOH_EHCI_CAPLENGTH 0x00
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#define R_IOH_EHCI_INSNREG01 0x94
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#define B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP (16)
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#define B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_MASK (0xff << B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP)
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#define B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP (0)
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#define B_IOH_EHCI_INSNREG01_IN_THRESHOLD_MASK (0xff << B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP)
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//
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// EHCI memory mapped registers offset from memory BAR0 + Cap length value.
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//
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#define R_IOH_EHCI_CONFIGFLAGS 0x40
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//---------------------------------------------------------------------------
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// Quark South Cluster USB Device definitions
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//---------------------------------------------------------------------------
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#define IOH_USBDEVICE_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM
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#define IOH_USBDEVICE_FUNCTION_NUMBER 0x02
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//
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// USB Device memory mapped registers offset from memory BAR0.
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//
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#define R_IOH_USBDEVICE_D_INTR_UDC_REG 0x40c
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#define R_IOH_USBDEVICE_D_INTR_MSK_UDC_REG 0x410
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#define B_IOH_USBDEVICE_D_INTR_MSK_UDC_REG_MASK1_MASK 0xff
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#define R_IOH_USBDEVICE_EP_INTR_UDC_REG 0x414
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#define R_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG 0x418
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#define B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_OUT_EP_MASK 0x000f0000
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#define B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_IN_EP_MASK 0x0000000f
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//---------------------------------------------------------------------------
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// Quark South Cluster 10/100 Mbps Ethernet Device definitions.
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//---------------------------------------------------------------------------
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#define IOH_MAC0_BUS_NUMBER IOH_BUS
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#define IOH_MAC0_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM
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#define IOH_MAC0_FUNCTION_NUMBER 0x06
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#define IOH_MAC1_BUS_NUMBER IOH_BUS
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#define IOH_MAC1_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM
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#define IOH_MAC1_FUNCTION_NUMBER 0x07
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//
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// MAC Device PCI config registers.
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//
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#define R_IOH_MAC_DEVICE_ID 0x02
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#define V_IOH_MAC_VENDOR_ID INTEL_VENDOR_ID
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#define R_IOH_MAC_DEVICE_ID 0x02
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#define V_IOH_MAC_DEVICE_ID 0x0937
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#define R_IOH_MAC_COMMAND 0x04
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#define B_IOH_MAC_COMMAND_BME BIT2
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#define B_IOH_MAC_COMMAND_MSE BIT1
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#define B_IOH_MAC_COMMAND_ISE BIT0
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#define R_IOH_MAC_MEMBAR 0x10
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#define B_IOH_MAC_MEMBAR_ADDRESS_MASK 0xFFFFF000
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//
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// LAN Device memory mapped registers offset from memory BAR0.
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//
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#define R_IOH_MAC_GMAC_REG_8 0x20
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#define B_IOH_MAC_USERVER_MASK 0x0000FF00
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#define B_IOH_MAC_SNPSVER_MASK 0x000000FF
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#define R_IOH_MAC_GMAC_REG_16 0x40
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#define B_IOH_MAC_ADDRHI_MASK 0x0000FFFF
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#define B_IOH_MAC_AE BIT31
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#define R_IOH_MAC_GMAC_REG_17 0x44
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#define B_IOH_MAC_ADDRLO_MASK 0xFFFFFFFF
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//---------------------------------------------------------------------------
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// Quark I2C / GPIO definitions
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//---------------------------------------------------------------------------
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#define V_IOH_I2C_GPIO_VENDOR_ID INTEL_VENDOR_ID
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#define V_IOH_I2C_GPIO_DEVICE_ID 0x0934
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#define R_IOH_I2C_MEMBAR 0x10
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#define B_IOH_I2C_GPIO_MEMBAR_ADDR_MASK 0xFFFFF000 // [31:12].
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#define GPIO_SWPORTA_DR 0x00
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#define GPIO_SWPORTA_DDR 0x04
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#define GPIO_INTEN 0x30
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#define GPIO_INTMASK 0x34
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#define GPIO_INTTYPE_LEVEL 0x38
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#define GPIO_INT_POLARITY 0x3C
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#define GPIO_INTSTATUS 0x40
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#define GPIO_RAW_INTSTATUS 0x44
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#define GPIO_DEBOUNCE 0x48
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#define GPIO_PORTA_EOI 0x4C
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#define GPIO_EXT_PORTA 0x50
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#define GPIO_EXT_PORTB 0x54
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#define GPIO_LS_SYNC 0x60
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#define GPIO_CONFIG_REG2 0x70
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#define GPIO_CONFIG_REG1 0x74
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//---------------------------------------------------------------------------
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// Quark South Cluster UART definitions.
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//---------------------------------------------------------------------------
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#define R_IOH_UART_MEMBAR 0x10
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#define B_IOH_UART_MEMBAR_ADDRESS_MASK 0xFFFFF000 // [31:12].
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#endif
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