mirror of https://github.com/acidanthera/audk.git
7bed7ae6c5
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429 MSR is accessed in BaseXApicX2ApicLib. In TDX some MSRs are accessed directly from/to CPU. Some should be accessed via explicit requests from the host VMM using TDCALL(TDG.VP.VMCALL). This is done by the help of TdxLib. Please refer to [TDX] Section 18.1 TDX: https://software.intel.com/content/dam/develop/external/us/en/ documents/tdx-module-1.0-public-spec-v0.931.pdf Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com> |
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|---|---|---|
| .. | ||
| BaseUefiCpuLib | ||
| BaseXApicLib | ||
| BaseXApicX2ApicLib | ||
| CpuCacheInfoLib | ||
| CpuCommonFeaturesLib | ||
| CpuExceptionHandlerLib | ||
| CpuTimerLib | ||
| MicrocodeLib | ||
| MpInitLib | ||
| MpInitLibUp | ||
| MtrrLib | ||
| PlatformSecLibNull | ||
| RegisterCpuFeaturesLib | ||
| SecPeiDxeTimerLibUefiCpu | ||
| SmmCpuFeaturesLib | ||
| SmmCpuPlatformHookLibNull | ||
| SmmCpuRendezvousLib | ||
| VmgExitLibNull | ||