mirror of https://github.com/acidanthera/audk.git
127 lines
4.0 KiB
C
127 lines
4.0 KiB
C
/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#ifndef __PL390GIC_H
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#define __PL390GIC_H
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//
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// GIC definitions
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//
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//
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// GIC Distributor
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//
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#define ARM_GIC_ICDDCR 0x000 // Distributor Control Register
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#define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register
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#define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register
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// Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BITS (see GIC spec)
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#define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers
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#define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers
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#define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers
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#define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers
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#define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers
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#define ARM_GIC_ICDABR 0x300 // Active Bit Registers
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// Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BYTES
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#define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers
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// Each reg base below repeats for VE_NUM_ARM_GIC_INTERRUPTS
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#define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers
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#define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers
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#define ARM_GIC_ICDPPISR 0xD00 // PPI Status register
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// just one of these
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#define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register
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//
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// GIC Cpu interface
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//
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#define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register
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#define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register
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#define ARM_GIC_ICCBPR 0x08 // Binary Point Register
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#define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register
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#define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register
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#define ARM_GIC_ICCRPR 0x14 // Running Priority Register
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#define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register
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#define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register
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#define ARM_GIC_ICCIDR 0xFC // Identification Register
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#define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0
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#define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1
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#define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2
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// Bit-masks to configure the CPU Interface Control register
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#define ARM_GIC_ICCICR_ENABLE_SECURE 0x01
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#define ARM_GIC_ICCICR_ENABLE_NS 0x02
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#define ARM_GIC_ICCICR_ACK_CTL 0x04
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#define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08
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#define ARM_GIC_ICCICR_USE_SBPR 0x10
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//
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// GIC SEC interfaces
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//
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VOID
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EFIAPI
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ArmGicSetupNonSecure (
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IN INTN GicDistributorBase,
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IN INTN GicInterruptInterfaceBase
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);
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VOID
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EFIAPI
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ArmGicEnableInterruptInterface (
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IN INTN GicInterruptInterfaceBase
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);
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VOID
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EFIAPI
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ArmGicEnableDistributor (
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IN INTN GicDistributorBase
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);
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VOID
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EFIAPI
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ArmGicSendSgiTo (
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IN INTN GicDistributorBase,
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IN INTN TargetListFilter,
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IN INTN CPUTargetList
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);
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UINT32
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EFIAPI
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ArmGicAcknowledgeSgiFrom (
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IN INTN GicInterruptInterfaceBase,
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IN INTN CoreId
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);
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UINT32
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EFIAPI
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ArmGicAcknowledgeSgi2From (
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IN INTN GicInterruptInterfaceBase,
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IN INTN CoreId,
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IN INTN SgiId
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);
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UINTN
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EFIAPI
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ArmGicSetPriorityMask (
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IN INTN GicInterruptInterfaceBase,
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IN INTN PriorityMask
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);
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#endif
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