mirror of https://github.com/acidanthera/audk.git
525 lines
16 KiB
C
525 lines
16 KiB
C
/** @file
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "PciEmulation.h"
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EMBEDDED_EXTERNAL_DEVICE *gTPS65950;
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#define HOST_CONTROLLER_OPERATION_REG_SIZE 0x44
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typedef struct {
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ACPI_HID_DEVICE_PATH AcpiDevicePath;
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PCI_DEVICE_PATH PciDevicePath;
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EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
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} EFI_PCI_IO_DEVICE_PATH;
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typedef struct {
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UINT32 Signature;
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EFI_PCI_IO_DEVICE_PATH DevicePath;
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EFI_PCI_IO_PROTOCOL PciIoProtocol;
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PCI_TYPE00 *ConfigSpace;
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PCI_ROOT_BRIDGE RootBridge;
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UINTN Segment;
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} EFI_PCI_IO_PRIVATE_DATA;
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#define EFI_PCI_IO_PRIVATE_DATA_SIGNATURE SIGNATURE_32('p', 'c', 'i', 'o')
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#define EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(a) CR(a, EFI_PCI_IO_PRIVATE_DATA, PciIoProtocol, EFI_PCI_IO_PRIVATE_DATA_SIGNATURE)
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EFI_PCI_IO_DEVICE_PATH PciIoDevicePathTemplate =
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{
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{
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{ ACPI_DEVICE_PATH, ACPI_DP, sizeof (ACPI_HID_DEVICE_PATH), 0},
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EISA_PNP_ID(0x0A03), // HID
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0 // UID
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},
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{
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{ HARDWARE_DEVICE_PATH, HW_PCI_DP, sizeof (PCI_DEVICE_PATH), 0},
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0,
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0
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},
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{ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, sizeof (EFI_DEVICE_PATH_PROTOCOL), 0}
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};
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STATIC
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VOID
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ConfigureUSBHost (
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VOID
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)
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{
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EFI_STATUS Status;
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UINT8 Data = 0;
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// Take USB host out of force-standby mode
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MmioWrite32 (UHH_SYSCONFIG, UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY
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| UHH_SYSCONFIG_CLOCKACTIVITY_ON
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| UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY
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| UHH_SYSCONFIG_ENAWAKEUP_ENABLE
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| UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN);
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MmioWrite32 (UHH_HOSTCONFIG, UHH_HOSTCONFIG_P3_CONNECT_STATUS_DISCONNECT
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| UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT
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| UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT
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| UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE
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| UHH_HOSTCONFIG_ENA_INCR16_ENABLE
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| UHH_HOSTCONFIG_ENA_INCR8_ENABLE
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| UHH_HOSTCONFIG_ENA_INCR4_ENABLE
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| UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_ON
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| UHH_HOSTCONFIG_P1_ULPI_BYPASS_ULPI_MODE);
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// USB reset (GPIO 147 - Port 5 pin 19) output high
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MmioAnd32 (GPIO5_BASE + GPIO_OE, ~BIT19);
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MmioWrite32 (GPIO5_BASE + GPIO_SETDATAOUT, BIT19);
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// Get the Power IC protocol
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Status = gBS->LocateProtocol (&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTPS65950);
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ASSERT_EFI_ERROR (Status);
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// Power the USB PHY
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Data = VAUX_DEV_GRP_P1;
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Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, VAUX2_DEV_GRP), 1, &Data);
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ASSERT_EFI_ERROR(Status);
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Data = VAUX_DEDICATED_18V;
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Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, VAUX2_DEDICATED), 1, &Data);
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ASSERT_EFI_ERROR (Status);
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// Enable power to the USB hub
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Status = gTPS65950->Read (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3, LEDEN), 1, &Data);
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ASSERT_EFI_ERROR (Status);
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// LEDAON controls the power to the USB host, PWM is disabled
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Data &= ~LEDAPWM;
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Data |= LEDAON;
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Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3, LEDEN), 1, &Data);
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ASSERT_EFI_ERROR (Status);
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}
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EFI_STATUS
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PciIoPollMem (
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IN EFI_PCI_IO_PROTOCOL *This,
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IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
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IN UINT8 BarIndex,
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IN UINT64 Offset,
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IN UINT64 Mask,
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IN UINT64 Value,
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IN UINT64 Delay,
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OUT UINT64 *Result
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)
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{
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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EFI_STATUS
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PciIoPollIo (
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IN EFI_PCI_IO_PROTOCOL *This,
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IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
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IN UINT8 BarIndex,
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IN UINT64 Offset,
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IN UINT64 Mask,
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IN UINT64 Value,
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IN UINT64 Delay,
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OUT UINT64 *Result
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)
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{
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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EFI_STATUS
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PciIoMemRead (
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IN EFI_PCI_IO_PROTOCOL *This,
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IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
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IN UINT8 BarIndex,
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IN UINT64 Offset,
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IN UINTN Count,
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IN OUT VOID *Buffer
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)
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{
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EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
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return PciRootBridgeIoMemRead (&Private->RootBridge.Io,
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(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
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Private->ConfigSpace->Device.Bar[BarIndex] + Offset,
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Count,
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Buffer
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);
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}
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EFI_STATUS
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PciIoMemWrite (
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IN EFI_PCI_IO_PROTOCOL *This,
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IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
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IN UINT8 BarIndex,
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IN UINT64 Offset,
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IN UINTN Count,
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IN OUT VOID *Buffer
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)
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{
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EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
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return PciRootBridgeIoMemWrite (&Private->RootBridge.Io,
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(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
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Private->ConfigSpace->Device.Bar[BarIndex] + Offset,
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Count,
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Buffer
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);
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}
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EFI_STATUS
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PciIoIoRead (
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IN EFI_PCI_IO_PROTOCOL *This,
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IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
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IN UINT8 BarIndex,
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IN UINT64 Offset,
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IN UINTN Count,
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IN OUT VOID *Buffer
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)
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{
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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EFI_STATUS
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PciIoIoWrite (
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IN EFI_PCI_IO_PROTOCOL *This,
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IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
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IN UINT8 BarIndex,
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IN UINT64 Offset,
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IN UINTN Count,
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IN OUT VOID *Buffer
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)
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{
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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EFI_STATUS
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PciIoPciRead (
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IN EFI_PCI_IO_PROTOCOL *This,
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IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
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IN UINT32 Offset,
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IN UINTN Count,
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IN OUT VOID *Buffer
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)
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{
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EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
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return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,
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Count,
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TRUE,
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(PTR)(UINTN)Buffer,
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TRUE,
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(PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset)
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);
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}
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EFI_STATUS
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PciIoPciWrite (
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IN EFI_PCI_IO_PROTOCOL *This,
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IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
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IN UINT32 Offset,
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IN UINTN Count,
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IN OUT VOID *Buffer
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)
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{
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EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
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return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
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Count,
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TRUE,
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(PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset),
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TRUE,
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(PTR)(UINTN)Buffer
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);
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}
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EFI_STATUS
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PciIoCopyMem (
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IN EFI_PCI_IO_PROTOCOL *This,
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IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
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IN UINT8 DestBarIndex,
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IN UINT64 DestOffset,
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IN UINT8 SrcBarIndex,
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IN UINT64 SrcOffset,
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IN UINTN Count
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)
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{
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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EFI_STATUS
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PciIoMap (
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IN EFI_PCI_IO_PROTOCOL *This,
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IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,
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IN VOID *HostAddress,
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IN OUT UINTN *NumberOfBytes,
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OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
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OUT VOID **Mapping
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)
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{
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DMA_MAP_OPERATION DmaOperation;
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if (Operation == EfiPciIoOperationBusMasterRead) {
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DmaOperation = MapOperationBusMasterRead;
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} else if (Operation == EfiPciIoOperationBusMasterWrite) {
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DmaOperation = MapOperationBusMasterWrite;
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} else if (Operation == EfiPciIoOperationBusMasterCommonBuffer) {
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DmaOperation = MapOperationBusMasterCommonBuffer;
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} else {
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return EFI_INVALID_PARAMETER;
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}
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return DmaMap (DmaOperation, HostAddress, NumberOfBytes, DeviceAddress, Mapping);
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}
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EFI_STATUS
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PciIoUnmap (
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IN EFI_PCI_IO_PROTOCOL *This,
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IN VOID *Mapping
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)
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{
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return DmaUnmap (Mapping);
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}
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EFI_STATUS
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PciIoAllocateBuffer (
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IN EFI_PCI_IO_PROTOCOL *This,
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IN EFI_ALLOCATE_TYPE Type,
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IN EFI_MEMORY_TYPE MemoryType,
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IN UINTN Pages,
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OUT VOID **HostAddress,
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IN UINT64 Attributes
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)
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{
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if (Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) {
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// Check this
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return EFI_UNSUPPORTED;
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}
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return DmaAllocateBuffer (MemoryType, Pages, HostAddress);
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}
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EFI_STATUS
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PciIoFreeBuffer (
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IN EFI_PCI_IO_PROTOCOL *This,
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IN UINTN Pages,
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IN VOID *HostAddress
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)
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{
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return DmaFreeBuffer (Pages, HostAddress);
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}
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EFI_STATUS
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PciIoFlush (
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IN EFI_PCI_IO_PROTOCOL *This
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)
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{
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return EFI_SUCCESS;
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}
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EFI_STATUS
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PciIoGetLocation (
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IN EFI_PCI_IO_PROTOCOL *This,
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OUT UINTN *SegmentNumber,
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OUT UINTN *BusNumber,
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OUT UINTN *DeviceNumber,
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OUT UINTN *FunctionNumber
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)
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{
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EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
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if (SegmentNumber != NULL) {
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*SegmentNumber = Private->Segment;
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}
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if (BusNumber != NULL) {
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*BusNumber = 0xff;
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}
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if (DeviceNumber != NULL) {
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*DeviceNumber = 0;
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}
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if (FunctionNumber != NULL) {
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*FunctionNumber = 0;
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}
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return EFI_SUCCESS;
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}
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EFI_STATUS
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PciIoAttributes (
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IN EFI_PCI_IO_PROTOCOL *This,
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IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,
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IN UINT64 Attributes,
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OUT UINT64 *Result OPTIONAL
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)
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{
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switch (Operation) {
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case EfiPciIoAttributeOperationGet:
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case EfiPciIoAttributeOperationSupported:
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if (Result == NULL) {
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return EFI_INVALID_PARAMETER;
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}
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// We are not a real PCI device so just say things we kind of do
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*Result = EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER | EFI_PCI_DEVICE_ENABLE;
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break;
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case EfiPciIoAttributeOperationSet:
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case EfiPciIoAttributeOperationEnable:
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case EfiPciIoAttributeOperationDisable:
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// Since we are not a real PCI device no enable/set or disable operations exist.
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return EFI_SUCCESS;
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default:
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ASSERT (FALSE);
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return EFI_INVALID_PARAMETER;
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};
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return EFI_SUCCESS;
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}
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EFI_STATUS
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PciIoGetBarAttributes (
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IN EFI_PCI_IO_PROTOCOL *This,
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IN UINT8 BarIndex,
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OUT UINT64 *Supports, OPTIONAL
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OUT VOID **Resources OPTIONAL
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)
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{
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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EFI_STATUS
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PciIoSetBarAttributes (
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IN EFI_PCI_IO_PROTOCOL *This,
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IN UINT64 Attributes,
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IN UINT8 BarIndex,
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IN OUT UINT64 *Offset,
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IN OUT UINT64 *Length
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)
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{
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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EFI_PCI_IO_PROTOCOL PciIoTemplate =
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{
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PciIoPollMem,
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PciIoPollIo,
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PciIoMemRead,
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PciIoMemWrite,
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PciIoIoRead,
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PciIoIoWrite,
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PciIoPciRead,
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PciIoPciWrite,
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PciIoCopyMem,
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PciIoMap,
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PciIoUnmap,
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PciIoAllocateBuffer,
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PciIoFreeBuffer,
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PciIoFlush,
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PciIoGetLocation,
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PciIoAttributes,
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PciIoGetBarAttributes,
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PciIoSetBarAttributes,
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0,
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0
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};
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EFI_STATUS
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EFIAPI
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PciEmulationEntryPoint (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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EFI_HANDLE Handle;
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EFI_PCI_IO_PRIVATE_DATA *Private;
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UINT8 CapabilityLength;
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UINT8 PhysicalPorts;
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UINTN Count;
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//Configure USB host for OMAP3530.
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ConfigureUSBHost();
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// Create a private structure
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Private = AllocatePool(sizeof(EFI_PCI_IO_PRIVATE_DATA));
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if (Private == NULL) {
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Status = EFI_OUT_OF_RESOURCES;
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return Status;
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}
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Private->Signature = EFI_PCI_IO_PRIVATE_DATA_SIGNATURE; // Fill in signature
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Private->RootBridge.Signature = PCI_ROOT_BRIDGE_SIGNATURE; // Fake Root Bridge structure needs a signature too
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Private->RootBridge.MemoryStart = USB_EHCI_HCCAPBASE; // Get the USB capability register base
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Private->Segment = 0; // Default to segment zero
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// Find out the capability register length and number of physical ports.
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CapabilityLength = MmioRead8(Private->RootBridge.MemoryStart);
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PhysicalPorts = (MmioRead32 (Private->RootBridge.MemoryStart + 0x4)) & 0x0000000F;
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// Calculate the total size of the USB registers.
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Private->RootBridge.MemorySize = CapabilityLength + (HOST_CONTROLLER_OPERATION_REG_SIZE + ((4 * PhysicalPorts) - 1));
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// Enable Port Power bit in Port status and control registers in EHCI register space.
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// Port Power Control (PPC) bit in the HCSPARAMS register is already set which indicates
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// host controller implementation includes port power control.
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for (Count = 0; Count < PhysicalPorts; Count++) {
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MmioOr32 ((Private->RootBridge.MemoryStart + CapabilityLength + HOST_CONTROLLER_OPERATION_REG_SIZE + 4*Count), 0x00001000);
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}
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// Create fake PCI config space.
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Private->ConfigSpace = AllocateZeroPool(sizeof(PCI_TYPE00));
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if (Private->ConfigSpace == NULL) {
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Status = EFI_OUT_OF_RESOURCES;
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FreePool(Private);
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return Status;
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}
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// Configure PCI config space
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Private->ConfigSpace->Hdr.VendorId = 0x3530;
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Private->ConfigSpace->Hdr.DeviceId = 0x3530;
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Private->ConfigSpace->Hdr.ClassCode[0] = 0x20;
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Private->ConfigSpace->Hdr.ClassCode[1] = 0x03;
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Private->ConfigSpace->Hdr.ClassCode[2] = 0x0C;
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Private->ConfigSpace->Device.Bar[0] = Private->RootBridge.MemoryStart;
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Handle = NULL;
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// Unique device path.
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CopyMem(&Private->DevicePath, &PciIoDevicePathTemplate, sizeof(PciIoDevicePathTemplate));
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Private->DevicePath.AcpiDevicePath.UID = 0;
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// Copy protocol structure
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CopyMem(&Private->PciIoProtocol, &PciIoTemplate, sizeof(PciIoTemplate));
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Status = gBS->InstallMultipleProtocolInterfaces(&Handle,
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&gEfiPciIoProtocolGuid, &Private->PciIoProtocol,
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&gEfiDevicePathProtocolGuid, &Private->DevicePath,
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NULL);
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if (EFI_ERROR(Status)) {
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DEBUG((EFI_D_ERROR, "PciEmulationEntryPoint InstallMultipleProtocolInterfaces() failed.\n"));
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}
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return Status;
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}
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